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channel_route.py
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Remove EOL whitespace globally
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2020-11-03 06:29:17 -08:00 |
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contact.py
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Remove EOL whitespace globally
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2020-11-03 06:29:17 -08:00 |
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custom_cell_properties.py
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Set default port map
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2020-11-24 13:27:11 -08:00 |
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custom_layer_properties.py
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Remove EOL whitespace globally
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2020-11-03 06:29:17 -08:00 |
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delay_data.py
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Remove EOL whitespace globally
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2020-11-03 06:29:17 -08:00 |
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design.py
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Can redefine number of ports in custom_cell_properties
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2020-11-21 08:05:49 -08:00 |
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errors.py
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Add exception errors file
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2020-04-08 16:55:45 -07:00 |
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geometry.py
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Small bug fixes related to new name mapping.
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2020-11-16 13:42:42 -08:00 |
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graph_util.py
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Added debug measurements along main delay paths in SRAM. WIP.
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2020-11-17 12:43:17 -08:00 |
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hierarchy_design.py
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Merge multiple cell_name fix.
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2020-11-18 16:27:28 -08:00 |
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hierarchy_layout.py
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Use internal pin names in path names for signal traces.
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2020-11-19 08:45:09 -08:00 |
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hierarchy_spice.py
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Many edits.
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2020-11-22 08:24:47 -08:00 |
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lef.py
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Add PDK layer names to tech file
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2020-11-09 09:10:43 -08:00 |
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pin_layout.py
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Clean up invalid routing layer error message
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2020-11-12 09:43:08 -08:00 |
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power_data.py
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Move classes to individual file.
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2019-07-16 15:18:04 -07:00 |
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route.py
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Remove EOL whitespace globally
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2020-11-03 06:29:17 -08:00 |
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utils.py
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Use bitcell_base for all bitcells. Fix missing setup_bitcell call
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2020-11-02 17:00:15 -08:00 |
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vector.py
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Remove EOL whitespace globally
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2020-11-03 06:29:17 -08:00 |
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verilog.py
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PEP8 cleanup
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2020-11-17 16:56:00 -08:00 |
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wire.py
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Remove EOL whitespace globally
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2020-11-03 06:29:17 -08:00 |
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wire_path.py
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Remove EOL whitespace globally
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2020-11-03 06:29:17 -08:00 |
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wire_spice_model.py
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Remove EOL whitespace globally
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2020-11-03 06:29:17 -08:00 |
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