mrg 5ee3f4cc66 Many edits. ...

Use internal vdd/gnd names.
Refactor getters in bitcell to base class.
Add BIAS signal type.

2020-11-22 08:24:47 -08:00

..

channel_route.py

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

contact.py

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

custom_cell_properties.py

Many edits.

2020-11-22 08:24:47 -08:00

custom_layer_properties.py

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

delay_data.py

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

design.py

Can redefine number of ports in custom_cell_properties

2020-11-21 08:05:49 -08:00

errors.py

Add exception errors file

2020-04-08 16:55:45 -07:00

geometry.py

Small bug fixes related to new name mapping.

2020-11-16 13:42:42 -08:00

graph_util.py

Added debug measurements along main delay paths in SRAM. WIP.

2020-11-17 12:43:17 -08:00

hierarchy_design.py

Merge multiple cell_name fix.

2020-11-18 16:27:28 -08:00

hierarchy_layout.py

Use internal pin names in path names for signal traces.

2020-11-19 08:45:09 -08:00

hierarchy_spice.py

Many edits.

2020-11-22 08:24:47 -08:00

lef.py

Add PDK layer names to tech file

2020-11-09 09:10:43 -08:00

pin_layout.py

Clean up invalid routing layer error message

2020-11-12 09:43:08 -08:00

power_data.py

Move classes to individual file.

2019-07-16 15:18:04 -07:00

route.py

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

utils.py

Use bitcell_base for all bitcells. Fix missing setup_bitcell call

2020-11-02 17:00:15 -08:00

vector.py

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

verilog.py

PEP8 cleanup

2020-11-17 16:56:00 -08:00

wire_path.py

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

wire_spice_model.py

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

wire.py

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00