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OpenRAM
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239 Commits

Author SHA1 Message Date
Bastian Koppelmann 1380cbc50c technology: Add tech_module to all technologies 
this allows each technology to override each cell class.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2019-12-16 16:51:41 +01:00
Matt Guthaus 3ad7c8a8b5 Fix freepdk45 tech layer stacks 2019-12-13 14:25:00 -08:00
Matt Guthaus e048ada23c Abstract basic DRC checks 2019-12-11 17:56:55 -08:00
Matthew Guthaus d2cbc46527 Fix error 2019-12-06 00:05:26 +00:00
Matthew Guthaus 7397f110c5 Add bbox for special DRC rule boundary 2019-12-05 23:14:25 +00:00
Matt Guthaus 69bb245f28 Updates to gdsMill/tech layers 
Create active and poly contact types.
Define standard cell boundary option.
DataType and PurposeLayer are the same. Text must have type 0.
Remove vector from vlsiLayout. More debug in reader.
 2019-12-04 16:12:53 -08:00
Matt Guthaus 6ef1b6a4ec Blackbox option for DRC waivers 2019-11-29 15:50:32 -08:00
Matt Guthaus 2a912dab7a Remove unused config files 2019-11-29 12:35:35 -08:00
Matt Guthaus d511f648c6 Move DRC/LVS/PEX tools to tech file. 2019-11-29 12:01:33 -08:00
Matt Guthaus 102758881a Use layer instead of special flags for wells 2019-11-26 13:22:52 -08:00
Matthew Guthaus 131f4bda4a Add layer-purpose GDS support. Various PEP8 fixes. 2019-11-14 18:17:20 +00:00
Matt Guthaus ecbed870c0 Remove blockage layer. 2019-10-30 06:54:11 -07:00
Matt Guthaus 38213d998f Add separate layer and purpose pairs to tech layers. 2019-10-25 10:03:25 -07:00
Matt Guthaus 4c3b171b72 Share nominal temperature and voltage. Nominal instead of typical. 2019-09-04 16:53:58 -07:00
Matt Guthaus 585ce63dff Removing unused tech parms. Simplifying redundant parms. 2019-09-04 16:08:18 -07:00
Matt Guthaus 2af72db5dc Add comment layer to display.drf so it is included in .lyp file. 2019-08-27 08:51:34 -07:00
Matt Guthaus fc0fe91bb4 Added auto-converted lyp files to use klayout for viewing results 2019-08-26 10:41:14 -07:00
jsowash d5e331d4f3 Connected en together in write_mask_and_array. 2019-08-09 14:27:53 -07:00
Matt Guthaus c8c4d05bba Fix some regression fails. 2019-07-25 14:18:08 -07:00
mrg ae9dbe203d Add freepdk45 dummy cells 2019-07-03 14:53:44 -07:00
Hunter Nichols 4e08e2da87 Merged and fixed conflicts with dev 2019-06-25 16:55:50 -07:00
Hunter Nichols 33c17ac41c Moved manual delay chain declarations from tech files to options. 2019-06-25 15:45:02 -07:00
Matt Guthaus a234b0af88 Fix space before comment 2019-06-14 08:43:41 -07:00
Matt Guthaus 0f03553689 Update copyright to correct years. 2019-05-06 06:50:15 -07:00
Matt Guthaus e071e53090 Add comments on gds units in tech files. 2019-04-30 10:13:13 -07:00
Matt Guthaus 8b1cd57867 Change contact display wqfrom black X to green solid. 2019-04-29 14:08:10 -07:00
Matt Guthaus 3f9a987e51 Update copyright. Add header to all OpenRAM files. 2019-04-26 12:33:53 -07:00
Matt Guthaus 2c01daae8d Remove outdated SRAM layout virtuoso library 2019-04-26 09:10:48 -07:00
Hunter Nichols 25c034f85d Added more accurate bitline delay capacitance estimations 2019-04-09 01:56:32 -07:00
Hunter Nichols edac60d2a8 Merged with dev and fixed conflicts. 2019-04-03 16:45:01 -07:00
Hunter Nichols cc5b347f42 Added analyical model test which compares measured delay to model delay. 2019-04-03 16:26:20 -07:00
Hunter Nichols f6eefc1728 Added updated analytical characterization with combined models 2019-04-02 01:09:31 -07:00
Matt Guthaus 8b1787a733 Add SVRF EULA to FreePDK45 tech dir 2019-03-15 03:39:51 -07:00
Matt Guthaus d178801882 Simplify tech organization and import 2019-03-06 07:41:38 -08:00
Hunter Nichols 0e96648211 Added linear corner factors in analytical delay model. 2019-03-04 00:42:18 -08:00
Hunter Nichols 816669b9ca Merge branch 'dev' into multiport_characterization 2019-02-26 22:48:39 -08:00
Matt Guthaus be741a6828 Fix mising file 2019-02-24 11:04:56 -08:00
Matt Guthaus 9b785cd535 Fix error in cell width. Fix escape warning. 2019-02-24 10:48:54 -08:00
Matt Guthaus 6cdc870091 Copy 1rw/1r cell to 1w/1r. 2019-02-24 09:54:45 -08:00
Hunter Nichols 8c1fe253d5 Added variable fanouts to delay testing. 2019-02-13 22:24:58 -08:00
Hunter Nichols 6d3884d60d Added corner data collection. 2019-01-22 16:40:46 -08:00
Hunter Nichols 8eb4812e16 Made parasitic delay parameter in Freepdk45 more accurate, added stage names to delay model. 2018-12-17 23:32:02 -08:00
Hunter Nichols 51b1bd46da Added option to use delay chain size defined in tech.py 2018-12-14 18:02:19 -08:00
Hunter Nichols 97fc37aec1 Added checks for the bitline voltage at sense amp enable 50%. 2018-12-12 23:59:32 -08:00
Hunter Nichols 1e87a0efd2 Re-added new width 1rw,1r bitcells with flattened gds. 2018-12-05 20:43:10 -08:00
Hunter Nichols 009f6e94ea Reverted gds/sp to reprevious widths. 2018-12-05 17:42:31 -08:00
Hunter Nichols 05773ad16e Altered 1rw,1r cell and replica to match tx widths pbitcell in freepdk45 2018-11-14 11:53:13 -08:00
Hunter Nichols bad55cfd05 Merged with dev. Fixed merge conflict. 2018-11-09 17:18:19 -08:00
Matt Guthaus 83aadc47c9 Remove layer 230 labels from library cells 2018-11-09 11:12:31 -08:00
Matt Guthaus 05c25eb506 Remove layer 230 labels from library cells 2018-11-09 11:08:20 -08:00
Matt Guthaus 9fe64b486c Remove layer 230 labels from library cells 2018-11-09 11:02:19 -08:00
Hunter Nichols 8957c556db Added sense amp enable delay calculation. 2018-11-08 23:54:18 -08:00
Hunter Nichols b8061d3a4e Added initial code for determining the logical effort delay of the wordline. 2018-11-08 23:54:18 -08:00
Matt Guthaus c01f0f5274 Merge branch 'dev' into fix_rbl_cell_connections 2018-11-05 16:38:46 -08:00
Matt Guthaus 0ec16c2b68 Modify replica cell spice in FreePDK45 to short Qbar to vdd 2018-11-05 11:42:42 -08:00
Matt Guthaus de6d9d4699 Change freepdk45 rbl cell too. 2018-11-05 11:02:11 -08:00
Matt Guthaus 3c5dc70ede Comment spice cells. Change replica to short Q to vdd instead of Qbar to gnd. 2018-11-05 10:59:08 -08:00
Hunter Nichols 7461f2b1bf Merged with dev. 2018-11-02 17:22:09 -07:00
Matt Guthaus 6d48bdf55a Merge branch 'supply_routing' into dev 2018-11-02 11:51:32 -07:00
Matt Guthaus 4e09f0a944 Change layer text to comment to avoid glade reserved keyword 2018-11-02 10:58:00 -07:00
Hunter Nichols b00fc040a3 Added replica 1rw+1r cell python modules. Also added drc/lvs checks in replica bitline, but test is failing due to pin error in freepdk45 and metal spacing error in scmos. 2018-11-01 12:29:49 -07:00
Hunter Nichols 9321f0461b Fixed error in control logic test. Added gds/sp for replica cell 1rw+1r. 2018-10-31 00:06:34 -07:00
Hunter Nichols 6efe0f56c2 Added gds/sp for scn4m 1rw+1r bitcell. Passes DRC/LVS in both technologies for single and array. 2018-10-26 00:08:13 -07:00
Hunter Nichols 8e243258e4 Added updated 1rw 1r bitcell with a text boundary. Added bitcell array test for the bitcell. 2018-10-26 00:08:12 -07:00
Hunter Nichols 016604f846 Fixed spacing in golden lib files. Added column mux into analytical model. 2018-10-24 00:16:26 -07:00
Hunter Nichols 62439bdac6 Fixed merge conflicts with sram.py 2018-10-22 17:29:14 -07:00
Hunter Nichols 4f08062268 Added custom 1rw+1r bitcell. Testing are currently failing. 2018-10-22 17:02:21 -07:00
Matt Guthaus 4bf1e206e2 Merge branch 'dev' into supply_routing 2018-10-17 09:47:18 -07:00
Michael Timothy Grimes e60deddfea adding 6T transistor size parameters to tech files for use in pbitcell. 2018-10-17 07:28:56 -07:00
Matt Guthaus 4932d83afc Add design rules classes for complex design rules 2018-10-12 09:44:36 -07:00
Matt Guthaus 823cb04b80 Fix metal4 rules in FreePDK45. Multiport still needs updating. 2018-10-11 09:56:15 -07:00
Matt Guthaus 1ed74cd571 Add minarea_metal4 in freepdk45 2018-10-10 15:33:16 -07:00
Matt Guthaus f8fc7c12b3 Remove ms_flop and replace with dff. Might break setup_hold tests. 2018-09-13 11:02:28 -07:00
Hunter Nichols 5dfa8bc2c6 Fixed known typos of the word transition. 2018-09-10 14:27:26 -07:00
Matt Guthaus 93b24d8c85 Merge remote-tracking branch 'origin/dev' into supply_routing 2018-09-05 11:05:41 -07:00
Matt Guthaus 2a27fbc98e Fix temp directory preservation option. 
Make labels in freepdk45 replica bitcell lower case.
 2018-09-05 10:02:12 -07:00
Matt Guthaus 378993ca22 Found rotate bug in transformCoordinate. Cleaned up transFlags. 2018-09-04 16:35:40 -07:00
Matt Guthaus d721fae5b0 Change labels in replica cell for freepdk45 too 2018-09-04 14:33:14 -07:00
Matt Guthaus e36452622c Preserve same order of design rules in each tech file 2018-08-29 16:12:06 -07:00
Michael Timothy Grimes 1f53a82d56 Fixed name for poly_to_polycontact rule. Previously said poly_to_contactpoly in error. 2018-08-29 15:04:17 -07:00
Michael Timothy Grimes 0182309f92 Editting comment on rule 5.5.b in scmos tech file. Adding complimentary rule to freepdk45 tech file. 2018-08-29 14:51:50 -07:00
Matt Guthaus 49bee6a96e Remove OEB signal since we split DIN/DOUT ports 2018-08-13 14:09:49 -07:00
Matt Guthaus 368ab718d6 Change internal nets of 6T cell and write driver to have useful names for debugging. 2018-07-26 11:26:47 -07:00
Michael Timothy Grimes d8cb3653e0 changing case of pins in handmade cell_6t for freepdk45 2018-05-22 14:19:26 -07:00
Matt Guthaus 85b7b73903 Flip sense amp y axis 2018-04-23 10:19:26 -07:00
Matt Guthaus 269d553857 Move sense amp to tri gate routing to M3... not ideal. 2018-04-23 09:14:18 -07:00
Matt Guthaus e1f4c933e1 Flip sense amp and increase pin size 2018-04-20 17:04:26 -07:00
Matt Guthaus c75eafe085 Fix some errors 2018-04-18 09:37:33 -07:00
Matt Guthaus e2f93a0a99 Fix via overlap DRC error 2018-04-11 15:48:40 -07:00
Matt Guthaus ef99d13f1b Fix via overlap DRC error 2018-04-11 15:46:44 -07:00
Matt Guthaus 6640d3491d Tri gate and array supply to M2 and M3 2018-04-11 15:11:47 -07:00
Matt Guthaus 06c132b695 Fix drc overlap error 2018-04-11 15:00:56 -07:00
Matt Guthaus 21bc5b7d05 Fix drc overlap error 2018-04-11 14:59:04 -07:00
Matt Guthaus 14ff20fc9e Fix drc overlap error 2018-04-11 14:56:59 -07:00
Matt Guthaus d1862eda90 Fix drc overlap error 2018-04-11 14:55:04 -07:00
Matt Guthaus 46c18f53ba Add M2 vias in ms_flop 2018-04-11 14:10:57 -07:00
Matt Guthaus 0e6720be66 Fix write driver gnd pin layer text 2018-04-11 09:34:13 -07:00
Matt Guthaus 4f8ab78ee2 Change write driver supply pins to M2 2018-04-11 09:29:54 -07:00
Matt Guthaus 80829aa0af Sense amp vdd/gnd to M2 2018-04-06 17:15:36 -07:00
Matt Guthaus a35fc1f339 Add contact to cell6t and replica. 2018-04-04 13:18:12 -07:00
Matt Guthaus a0bf5345f8 Mostly working for 1 bank. 2018-03-23 08:14:26 -07:00
Matt Guthaus 1f81b24e96 Single bank passing DRC and LVS again. 
Unfold hierarchical decoder to improve routability.
 2018-03-23 08:13:10 -07:00
Matt Guthaus c020d74f26 Add dff_buf and dff_array modules. 2018-03-23 08:11:51 -07:00
Matt Guthaus 8d9b79dfd8 Add dff_buf for buffered flop arrays. 2018-03-04 16:13:10 -08:00
Matt Guthaus 7293eb33bc Merge branch 'dev' of https://github.com/mguthaus/OpenRAM into dev 2018-03-02 10:30:16 -08:00
Matt Guthaus ae2dbb4cd5 Add display techfiles from NCSU PDKs. 2018-03-02 10:30:03 -08:00
Hunter Nichols e6d6680da1 Fixed conflict in delay.py 2018-02-27 13:02:22 -08:00
Matt Guthaus 2b839d34a3 Get rid of netgen error of undefined dlatch. Fix sp_read to find correct subckt name and pins. 2018-02-27 08:59:46 -08:00
Hunter Nichols d0e6dc9ce7 First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level. 2018-02-26 16:32:28 -08:00
Matt Guthaus 9d1f31467e Move internal power to clock pin. Differentiate leakge power when CSb is high. 2018-02-23 12:21:32 -08:00
Hunter Nichols d4a0f48d4f Added power calculations for inverter. Still testing. 2018-02-21 19:51:21 -08:00
mguthaus 1297cb4e40 Convert dff to VTG transistors in 45nm. Correct pin order in dff library cell. 2018-02-16 10:40:05 -08:00
Matt Guthaus bab9ae8201 Fix off-grid pin and overlap problems for pins in freepdk dff cell. 2018-02-15 17:54:26 -08:00
Matt Guthaus e66a37c916 Put DFF pins on 2.5nm grid in 45nm. 2018-02-15 11:08:57 -08:00
Matt Guthaus 2d3acb03a1 Add bbox for dff in freepdk45 2018-02-14 17:04:31 -08:00
Matt Guthaus d89e49aecc Add metal2 pins to freepdk45 dff. 2018-02-14 16:58:41 -08:00
Matt Guthaus 0804a1eceb Add new DFF. Create DFF module. Start dff_array, not tested. 2018-02-14 15:16:28 -08:00
Matt Guthaus a12ebeed9f Add multiple process corners. Unit tests use nominal corner only. Add fake SCMOS nominal models, but they are broken. 2018-02-12 09:33:23 -08:00
Matt Guthaus f86985821a Begin modifications for corner-based characterization. Made stimuli.py a class. Golden output files are not updated. 2018-02-09 15:33:03 -08:00
Matt Guthaus fb90b8f5fe Fix pin nameon sense amp spice. Fix NAND2 bug in hierarchical decoder. 2018-02-02 14:08:56 -08:00
Matt Guthaus 64546ad3dd Change wen to en in spice lib files. Check lvs report insted of stdout with netgen. 2018-02-01 05:38:48 -08:00
Matt Guthaus 512448f9e8 Fix pin names to lower case. Fix write driver DRC errors and LVS error. 2018-01-31 17:37:16 -08:00
Matt Guthaus efa465757c Remove dead code ptx_port. 2018-01-19 16:19:05 -08:00
Matt Guthaus 1701eac1a9 Added workaround to import layouts into Magic. Select and well layers in active contacts. Fixed missing implant enclose active DRC rule in parameterized cells. 2018-01-11 10:24:44 -08:00
Matt Guthaus e95988c639 Document tech files. Remove unused/redundant rules. Made rule names consistent/simple. 2018-01-08 11:57:51 -08:00
Matt Guthaus 8df46abb30 Move nmos gate to the top of the ptx. 2017-12-01 08:31:16 -08:00
Matt Guthaus 257cd62d25 Remove tools from tech file and have search order preference like spice. 2017-11-14 15:27:03 -08:00
Matt Guthaus 3e0f39cd8e Skeleton code for indirect DRC/LVS/PEX tools. 2017-11-14 14:59:14 -08:00
Matt Guthaus e06e1691c8 Two bank SRAMs working in both technologies. 2017-09-29 16:22:13 -07:00
Matt Guthaus d17711c394 Fixed several LVS errors. Bank passes LVS for 2-way and 4-way, but not 1-way or 8-way. 2017-08-24 16:22:14 -07:00
Matt Guthaus cf940fb15d Development version of new pin data structure. Tests pass LVS/DRC except for bank level. 2017-08-23 15:02:15 -07:00
Matt Guthaus 20d8c0bc45 Improved characterizer. 2017-07-06 08:42:25 -07:00
Matt Guthaus 34e180b901 Analytical delay model from Bin Wu. Unit test not passing. 2017-05-30 12:50:07 -07:00
mguthaus 7ca5c0b34f Added zoom to technology file so labels in each tech are readable size. Made default size. 2017-05-23 16:18:11 -07:00
Matt Guthaus fef708cffd Add slash in layers.map 2016-11-18 15:05:17 -08:00
Matt Guthaus 8934c1d3a4 Fixed layer map in runset files 2016-11-18 11:21:12 -08:00
Matt Guthaus b51c124810 Moved spice path to technology setup files instead of tech file itself. 2016-11-09 13:29:33 -08:00
Matt Guthaus db8a675d90 Clean up tech files to remove old parameters moved to premade cell classes. 2016-11-09 11:35:32 -08:00
Matt Guthaus f48272bde6 RELEASE 1.0 2016-11-08 09:57:35 -08:00