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OpenRAM
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239 Commits

Author SHA1 Message Date
Hunter Nichols ebc91814e5 Fixed various issues with imported code from CACTI, added CACTI as an option for analytical sim, added placeholder names in tech files for CACTI 2021-07-12 15:48:47 -07:00
mrg 9720e5af29 Remove default array row/col multiple 2021-06-29 11:28:19 -07:00
Hunter Nichols 294ccf602e Merged with dev, addressed conflict in port data 2021-06-21 17:23:32 -07:00
Hunter Nichols 8ee6d3be6c Added more data for regression modules. 2021-06-21 17:21:00 -07:00
Jesse Cirimelli-Low 8346ad736e add dimension contraints to other tech files 2021-06-18 14:36:15 -07:00
Hunter Nichols 4ec2e1240f Merge branch 'dev' into automated_analytical_model 2021-06-09 15:45:41 -07:00
Hunter Nichols c50ffe70b3 Added more configs for model and respective data. 2021-06-09 15:42:15 -07:00
Hunter Nichols 7a60eabdfe Add more freepdk45 data from regression model. 2021-06-09 13:31:38 -07:00
Hunter Nichols 54639bbb94 Added more data for regression models 2021-06-04 13:37:21 -07:00
Jesse Cirimelli-Low 6705f99855 merge in dev 2021-05-28 14:06:23 -07:00
Hunter Nichols a53c6c51ed Added sim data for freepdk45 and removed stale data 2021-05-26 18:40:46 -07:00
Jesse Cirimelli-Low e976c4043b Merge branch 'dev' into laptop_checkpoint 2021-04-14 15:58:06 -07:00
ota2 15e57d89ca fix end subckt typo 2021-02-27 18:28:07 -05:00
ota2 8403749fec Add Q and Qbar labels 2021-02-27 18:27:08 -05:00
jcirimel b18e2eae8d remove debug lines and merge 2021-02-09 20:53:23 -08:00
jcirimel dbe8a7f1af fix pwell pin shape bug 2021-02-09 20:51:50 -08:00
Hunter Nichols df8d59f32e Merge branch 'dev' into automated_analytical_model 2021-02-01 01:49:45 -08:00
Matt Guthaus 4b1c359089 update copyright year. 2021-01-22 11:24:53 -08:00
Hunter Nichols 59200d1048 Added updated data for scmos, removed unused files. 2021-01-13 13:09:21 -08:00
Hunter Nichols ed3d39a1b8 Added updated model data with slews and loads. Changed linear regressions to account for additional models. 2021-01-13 13:04:34 -08:00
Hunter Nichols 32ad436153 Added freepdk45 data for linear regression 2020-12-22 15:19:31 -08:00
mrg 8021430122 Fix pbitcell erros 2020-11-13 15:55:55 -08:00
mrg c472a94f1e Rework bitcells. 
Name them 1port and 2port consistently.
Allow cell overrides to cell_1rw and cell_2rw or other.
Will use 2rw for 1rw/1r, 2rw, 1w/1r, etc.
 2020-11-13 10:07:40 -08:00
mrg cf63499e76 Convert bitcells to 1port and 2port 2020-11-13 08:09:21 -08:00
mrg a2f29e5edd Fix missing nand4_leakage #97 2020-11-12 09:48:08 -08:00
mrg 66633a843b Add PDK layer names to tech file 2020-11-09 09:10:43 -08:00
mrg da721a677d Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
mrg 611a4155b9 Add initial custom layer properties. 2020-10-27 15:11:04 -07:00
mrg ef310970bf Use new Google PDK lib 2020-10-12 15:46:11 -07:00
jcirimel 35eac54c0d update freepdk bitcell for pex 2020-08-17 17:47:43 -07:00
jcirimel 19f4e30989 change Qbar to Q_bar in freepdk45 bitcells 2020-08-04 15:21:54 -07:00
mrg 80070dff41 Move write_driver din left to avoid control signal in spare columns. 2020-07-16 14:47:14 -07:00
mrg 20324ab3c4 Revert write driver pin spacing 2020-06-28 14:55:58 -07:00
mrg e774314add Separate write driver pins by M3 pitch 2020-06-28 14:14:48 -07:00
mrg a7ee17eb2d Move output of sense amp to side like other techs 2020-06-26 15:29:27 -07:00
mrg cddb16dabc Separate active and poly contact to gate rule 2020-06-24 09:17:39 -07:00
mrg 157926960b Flip freepdk45 flop, dff_buf route layer change 2020-06-09 13:48:16 -07:00
mrg b7c66d7e07 Changes to simplify metal preferred directions and pitches. 
Changes to allow decoder height to be a 2x multiple of bitcell height.
Split of control logic tests.
Fixed track spacing in SRAM and channel router
PEP8 cleanup.
 2020-05-10 11:32:45 -07:00
Jesse Cirimelli-Low aedbc5f968 merge custom cell and module properties 2020-02-12 04:09:40 +00:00
Jesse Cirimelli-Low 18573c0e42 add module properties to other technologies 2020-02-05 22:25:35 +00:00
mrg 79391b84da Cleanup and rename vias. 2020-01-30 01:45:33 +00:00
Matt Guthaus 3147b99ce0 Merge remote-tracking branch 'bkoppelmann/bit-sym' into dev 2020-01-29 11:24:09 -08:00
Bastian Koppelmann df9f351a91 Add custom cell properties to technologies 
this is technology specific database to store data about the custom
design cells. For now it only contains on which axis the bitcells are
mirrored. This is a first step to support thin cells that need to be
mirrored on the x and y axis.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-01-28 15:46:14 +01:00
Bastian Koppelmann 407bd026ee tech: Make m3_stack the power_grid stack for FreePDK45/scn4m 
explicitly stating the power_grid makes people porting a new technology
aware of this option.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-01-28 12:06:38 +01:00
mrg 9beb0f4ece Add separate well design rules. 
Needed to fix various pgates with wells.
Did some cleanup of these gates as well.
 2020-01-23 19:43:41 +00:00
Matt Guthaus a8d370ee8c Improved comments in tech files 2019-12-20 16:35:31 -08:00
Matt Guthaus b7d78ec2ec Fix ptx active contact orientation to non-default M1 direction. 2019-12-19 12:54:10 -08:00
Matthew Guthaus 8e151553e4 Update contact types. 
Use preferred directions in tech files.
Programmatically generate based on interconnect stacks.
 2019-12-17 23:45:07 +00:00
Matt Guthaus 24546461ad Fix over-writing of active spacing rule. 2019-12-17 11:23:59 -08:00
Matt Guthaus ed28b4983b Clean up and generalize layer rules. 
Convert metalN to mN.
Generalize helper constants in modules for
space, width, enclose, etc.
Use layer stacks whever possible.
Try to remove drc() calls in liu of helper constants.
 2019-12-17 11:03:36 -08:00
Bastian Koppelmann 1380cbc50c technology: Add tech_module to all technologies 
this allows each technology to override each cell class.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2019-12-16 16:51:41 +01:00
Matt Guthaus 3ad7c8a8b5 Fix freepdk45 tech layer stacks 2019-12-13 14:25:00 -08:00
Matt Guthaus e048ada23c Abstract basic DRC checks 2019-12-11 17:56:55 -08:00
Matthew Guthaus d2cbc46527 Fix error 2019-12-06 00:05:26 +00:00
Matthew Guthaus 7397f110c5 Add bbox for special DRC rule boundary 2019-12-05 23:14:25 +00:00
Matt Guthaus 69bb245f28 Updates to gdsMill/tech layers 
Create active and poly contact types.
Define standard cell boundary option.
DataType and PurposeLayer are the same. Text must have type 0.
Remove vector from vlsiLayout. More debug in reader.
 2019-12-04 16:12:53 -08:00
Matt Guthaus 6ef1b6a4ec Blackbox option for DRC waivers 2019-11-29 15:50:32 -08:00
Matt Guthaus 2a912dab7a Remove unused config files 2019-11-29 12:35:35 -08:00
Matt Guthaus d511f648c6 Move DRC/LVS/PEX tools to tech file. 2019-11-29 12:01:33 -08:00
Matt Guthaus 102758881a Use layer instead of special flags for wells 2019-11-26 13:22:52 -08:00
Matthew Guthaus 131f4bda4a Add layer-purpose GDS support. Various PEP8 fixes. 2019-11-14 18:17:20 +00:00
Matt Guthaus ecbed870c0 Remove blockage layer. 2019-10-30 06:54:11 -07:00
Matt Guthaus 38213d998f Add separate layer and purpose pairs to tech layers. 2019-10-25 10:03:25 -07:00
Matt Guthaus 4c3b171b72 Share nominal temperature and voltage. Nominal instead of typical. 2019-09-04 16:53:58 -07:00
Matt Guthaus 585ce63dff Removing unused tech parms. Simplifying redundant parms. 2019-09-04 16:08:18 -07:00
Matt Guthaus 2af72db5dc Add comment layer to display.drf so it is included in .lyp file. 2019-08-27 08:51:34 -07:00
Matt Guthaus fc0fe91bb4 Added auto-converted lyp files to use klayout for viewing results 2019-08-26 10:41:14 -07:00
jsowash d5e331d4f3 Connected en together in write_mask_and_array. 2019-08-09 14:27:53 -07:00
Matt Guthaus c8c4d05bba Fix some regression fails. 2019-07-25 14:18:08 -07:00
mrg ae9dbe203d Add freepdk45 dummy cells 2019-07-03 14:53:44 -07:00
Hunter Nichols 4e08e2da87 Merged and fixed conflicts with dev 2019-06-25 16:55:50 -07:00
Hunter Nichols 33c17ac41c Moved manual delay chain declarations from tech files to options. 2019-06-25 15:45:02 -07:00
Matt Guthaus a234b0af88 Fix space before comment 2019-06-14 08:43:41 -07:00
Matt Guthaus 0f03553689 Update copyright to correct years. 2019-05-06 06:50:15 -07:00
Matt Guthaus e071e53090 Add comments on gds units in tech files. 2019-04-30 10:13:13 -07:00
Matt Guthaus 8b1cd57867 Change contact display wqfrom black X to green solid. 2019-04-29 14:08:10 -07:00
Matt Guthaus 3f9a987e51 Update copyright. Add header to all OpenRAM files. 2019-04-26 12:33:53 -07:00
Matt Guthaus 2c01daae8d Remove outdated SRAM layout virtuoso library 2019-04-26 09:10:48 -07:00
Hunter Nichols 25c034f85d Added more accurate bitline delay capacitance estimations 2019-04-09 01:56:32 -07:00
Hunter Nichols edac60d2a8 Merged with dev and fixed conflicts. 2019-04-03 16:45:01 -07:00
Hunter Nichols cc5b347f42 Added analyical model test which compares measured delay to model delay. 2019-04-03 16:26:20 -07:00
Hunter Nichols f6eefc1728 Added updated analytical characterization with combined models 2019-04-02 01:09:31 -07:00
Matt Guthaus 8b1787a733 Add SVRF EULA to FreePDK45 tech dir 2019-03-15 03:39:51 -07:00
Matt Guthaus d178801882 Simplify tech organization and import 2019-03-06 07:41:38 -08:00
Hunter Nichols 0e96648211 Added linear corner factors in analytical delay model. 2019-03-04 00:42:18 -08:00
Hunter Nichols 816669b9ca Merge branch 'dev' into multiport_characterization 2019-02-26 22:48:39 -08:00
Matt Guthaus be741a6828 Fix mising file 2019-02-24 11:04:56 -08:00
Matt Guthaus 9b785cd535 Fix error in cell width. Fix escape warning. 2019-02-24 10:48:54 -08:00
Matt Guthaus 6cdc870091 Copy 1rw/1r cell to 1w/1r. 2019-02-24 09:54:45 -08:00
Hunter Nichols 8c1fe253d5 Added variable fanouts to delay testing. 2019-02-13 22:24:58 -08:00
Hunter Nichols 6d3884d60d Added corner data collection. 2019-01-22 16:40:46 -08:00
Hunter Nichols 8eb4812e16 Made parasitic delay parameter in Freepdk45 more accurate, added stage names to delay model. 2018-12-17 23:32:02 -08:00
Hunter Nichols 51b1bd46da Added option to use delay chain size defined in tech.py 2018-12-14 18:02:19 -08:00
Hunter Nichols 97fc37aec1 Added checks for the bitline voltage at sense amp enable 50%. 2018-12-12 23:59:32 -08:00
Hunter Nichols 1e87a0efd2 Re-added new width 1rw,1r bitcells with flattened gds. 2018-12-05 20:43:10 -08:00
Hunter Nichols 009f6e94ea Reverted gds/sp to reprevious widths. 2018-12-05 17:42:31 -08:00
Hunter Nichols 05773ad16e Altered 1rw,1r cell and replica to match tx widths pbitcell in freepdk45 2018-11-14 11:53:13 -08:00
Hunter Nichols bad55cfd05 Merged with dev. Fixed merge conflict. 2018-11-09 17:18:19 -08:00
Matt Guthaus 83aadc47c9 Remove layer 230 labels from library cells 2018-11-09 11:12:31 -08:00
Matt Guthaus 05c25eb506 Remove layer 230 labels from library cells 2018-11-09 11:08:20 -08:00