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Altered 1rw,1r cell and replica to match tx widths pbitcell in freepdk45

This commit is contained in:
Hunter Nichols 2018-11-14 11:53:13 -08:00
parent 80bc5b49c1
commit 05773ad16e
4 changed files with 4 additions and 4 deletions
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technology/freepdk45/gds_lib/cell_1rw_1r.gds
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technology/freepdk45/gds_lib/replica_cell_1rw_1r.gds
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technology/freepdk45/sp_lib/cell_1rw_1r.sp vendored
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@ -6,8 +6,8 @@ MM7 RA_to_R_left Q_bar gnd gnd NMOS_VTG W=180.0n L=50n m=1
MM6 RA_to_R_left wl1 bl1 gnd NMOS_VTG W=180.0n L=50n m=1
MM5 Q wl0 bl0 gnd NMOS_VTG W=135.00n L=50n m=1
MM4 Q_bar wl0 br0 gnd NMOS_VTG W=135.00n L=50n m=1
MM1 Q Q_bar gnd gnd NMOS_VTG W=270.0n L=50n m=1
MM0 Q_bar Q gnd gnd NMOS_VTG W=270.0n L=50n m=1
MM1 Q Q_bar gnd gnd NMOS_VTG W=205.0n L=50n m=1
MM0 Q_bar Q gnd gnd NMOS_VTG W=205.0n L=50n m=1
MM3 Q Q_bar vdd vdd PMOS_VTG W=90n L=50n m=1
MM2 Q_bar Q vdd vdd PMOS_VTG W=90n L=50n m=1
.ENDS

4
technology/freepdk45/sp_lib/replica_cell_1rw_1r.sp vendored
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@ -6,8 +6,8 @@ MM7 RA_to_R_left vdd gnd gnd NMOS_VTG W=180.0n L=50n m=1
MM6 RA_to_R_left wl1 bl1 gnd NMOS_VTG W=180.0n L=50n m=1
MM5 Q wl0 bl0 gnd NMOS_VTG W=135.00n L=50n m=1
MM4 vdd wl0 br0 gnd NMOS_VTG W=135.00n L=50n m=1
MM1 Q vdd gnd gnd NMOS_VTG W=270.0n L=50n m=1
MM0 vdd Q gnd gnd NMOS_VTG W=270.0n L=50n m=1
MM1 Q vdd gnd gnd NMOS_VTG W=205.0n L=50n m=1
MM0 vdd Q gnd gnd NMOS_VTG W=205.0n L=50n m=1
MM3 Q vdd vdd vdd PMOS_VTG W=90n L=50n m=1
MM2 vdd Q vdd vdd PMOS_VTG W=90n L=50n m=1
.ENDS