mirror of https://github.com/VLSIDA/OpenRAM.git
Add display techfiles from NCSU PDKs.
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Matt Guthaus
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END OF TERMS AND CONDITIONS
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,47 @@
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These technology files are from the FreePDK45nm design kit.
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FreePDK 45nm verion 1.4 (2011-04-07)
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(Subversion Repository revision 173)
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Copyright 2007 - W. Rhett Davis, Paul Franzon, Michael Bucher,
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and Sunil Basavarajaiah, North Carolina State University
|
||||
Copyright 2008 - W. Rhett Davis, Michael Bucher, and Sunil Basavarajaiah,
|
||||
North Carolina State University (ncsu_basekit subtree)
|
||||
James Stine, and Ivan Castellanos,
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and Oklahoma State University (osu_soc subtree)
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Copyright 2011 - W. Rhett Davis, and Harun Demircioglu,
|
||||
North Carolina State University
|
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|
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SVRF Technology in this kit is licensed under the the agreement found
|
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in the file SVRF_EULA_06Feb09.txt in this directory. All other files
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are licensed under the Apache License, Version 2.0 (the "License");
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you may not use these files except in compliance with the License.
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
|
||||
|
||||
***** Welcome to the FreePDK 45nm Free, Open-Source Process Design Kit *****
|
||||
|
||||
This initiative is brought to you by the Semiconductor Research
|
||||
Corporation (SRC), the National Science Foundation (NSF), Silicon
|
||||
Integration Initiative (Si2), Mentor Graphics, and Synopsys.
|
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This version of the kit was created by Rhett Davis, Paul Franzon,
|
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Michael Bucher, Sunil Basavarajaiah, and Harun Demircioglu
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||||
of North Carolina State University, and James Stine and Ivan Castellanos
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of Oklahoma State University.
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Contributions and modifications to this kit are welcomed and encouraged.
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***** Contents *****
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ncsu_basekit/ Base kit for custom design
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osu_soc/ Standard-cell kit for synthesis, place, & route
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File diff suppressed because it is too large
Load Diff
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import os
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CWD = os.environ.get("OPENRAM_TECH") + "/freepdk45/tf"
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ui().importCds("default", CWD+"/display.drf", CWD+"/FreePDK45.tf", 1000, 1, CWD+"/layers.map")
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@ -0,0 +1,30 @@
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active drawing 1 0
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pwell drawing 2 0
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nwell drawing 3 0
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nimplant drawing 4 0
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pimplant drawing 5 0
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vtg drawing 6 0
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vth drawing 7 0
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thkox drawing 8 0
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poly drawing 9 0
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contact drawing 10 0
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metal1 drawing 11 0
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via1 drawing 12 0
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metal2 drawing 13 0
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via2 drawing 14 0
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metal3 drawing 15 0
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via3 drawing 16 0
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metal4 drawing 17 0
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via4 drawing 18 0
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metal5 drawing 19 0
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via5 drawing 20 0
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metal6 drawing 21 0
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via6 drawing 22 0
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metal7 drawing 23 0
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via7 drawing 24 0
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metal8 drawing 25 0
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via8 drawing 26 0
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metal9 drawing 27 0
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via9 drawing 28 0
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metal10 drawing 29 0
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text drawing 239 0
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@ -0,0 +1,714 @@
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drDefineDisplay(
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;( DisplayName )
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( display )
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)
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drDefineColor(
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;( DisplayName ColorsName Red Green Blue )
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( display white 255 255 255 )
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||||
( display yellow 255 255 0 )
|
||||
( display silver 217 230 255 )
|
||||
( display cream 255 255 204 )
|
||||
( display pink 255 191 242 )
|
||||
( display magenta 255 0 255 )
|
||||
( display lime 0 255 0 )
|
||||
( display tan 255 230 191 )
|
||||
( display cyan 0 255 255 )
|
||||
( display cadetBlue 57 191 255 )
|
||||
( display orange 255 128 0 )
|
||||
( display red 255 51 51 )
|
||||
( display purple 153 0 230 )
|
||||
( display green 0 204 102 )
|
||||
( display brown 191 64 38 )
|
||||
( display blue 51 77 255 )
|
||||
( display slate 140 140 166 )
|
||||
( display gold 217 204 0 )
|
||||
( display maroon 230 31 13 )
|
||||
( display violet 94 0 230 )
|
||||
( display forest 38 140 107 )
|
||||
( display chocolate 128 38 38 )
|
||||
( display navy 51 51 153 )
|
||||
( display black 0 0 0 )
|
||||
( display gray 204 204 217 )
|
||||
( display winColor1 166 166 166 )
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||||
( display winColor2 115 115 115 )
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( display winColor3 189 204 204 )
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||||
( display winColor4 204 204 204 )
|
||||
( display winColor5 199 199 199 )
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( display blinkRed 255 0 0 t )
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||||
( display blinkYellow 255 255 0 t )
|
||||
( display blinkWhite 255 255 255 t )
|
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( display winBack 224 224 224 )
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( display winFore 128 0 0 )
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( display winText 51 51 51 )
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)
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drDefineStipple(
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;( DisplayName StippleName Bitmap )
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( display dots ( ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
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( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) )
|
||||
( display dots1 ( ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) )
|
||||
( display hLine ( ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) ) )
|
||||
( display vLine ( ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) ) )
|
||||
( display cross ( ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) ) )
|
||||
( display grid ( ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
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( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) ) )
|
||||
( display stipple10 ( ( 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) )
|
||||
( display stipple11 ( ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) ) )
|
||||
( display dots2 ( ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) )
|
||||
( display dots4 ( ( 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 ) ) )
|
||||
( display dats5 ( ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) )
|
||||
)
|
||||
drDefineLineStyle(
|
||||
;( DisplayName LineStyle Size Pattern )
|
||||
( display solid 1 (1 ) )
|
||||
( display dashed 1 (1 1 1 0 0 1 1 1 ) )
|
||||
( display dots 1 (1 0 0 ) )
|
||||
( display dashDot 1 (1 1 1 0 0 1 0 0 ) )
|
||||
( display shortDash 1 (1 1 0 0 ) )
|
||||
( display doubleDash 1 (1 1 1 1 0 0 1 1 0 0 ) )
|
||||
( display hidden 1 (1 0 0 0 ) )
|
||||
( display thickLine 3 (1 1 1 ) )
|
||||
( display lineStyle0 1 (1 ) )
|
||||
( display lineStyle1 1 (1 1 1 0 1 1 1 0 1 1 1 0 1 1 0 1 ) )
|
||||
)
|
||||
drDefinePacket(
|
||||
;( DisplayName PacketName Stipple LineStyle Fill Outline [FillStyle])
|
||||
( display NwellNet dots4 thickLine slate slate outlineStipple)
|
||||
( display border stipple0 solid tan tan solid )
|
||||
( display y8 stipple0 solid gold gold solid )
|
||||
( display background stipple1 lineStyle0 black black outlineStipple)
|
||||
( display y9 stipple0 solid silver silver solid )
|
||||
( display Metal3Net dots4 solid navy navy outlineStipple)
|
||||
( display A1 stipple0 lineStyle0 winBack winBack solid )
|
||||
( display pin solid lineStyle0 red red solid )
|
||||
( display XPNet blank solid yellow yellow outline )
|
||||
( display hardFence stipple0 solid red red solid )
|
||||
( display PbaseNet dots4 solid yellow yellow outlineStipple)
|
||||
( display designFlow3 stipple1 lineStyle0 pink pink outlineStipple)
|
||||
( display A2 stipple0 lineStyle0 winBack winBack solid )
|
||||
( display Unrouted1 stipple0 lineStyle1 brown brown solid )
|
||||
( display RowLbl blank solid cyan cyan outline )
|
||||
( display edgeLayerPin stipple0 solid yellow yellow solid )
|
||||
( display instance blank solid winBack red outline )
|
||||
( display Nselect dots4 solid green green outlineStipple)
|
||||
( display snap stipple0 solid yellow yellow solid )
|
||||
( display pinAnt stipple0 solid red red solid )
|
||||
( display winAttentionText solid solid winText winText solid )
|
||||
( display designFlow2 stipple1 lineStyle0 purple purple outlineStipple)
|
||||
( display Unrouted2 stipple0 lineStyle1 red red solid )
|
||||
( display hilite blank solid white white outline )
|
||||
( display P2Con solid lineStyle0 orange orange solid )
|
||||
( display designFlow1 stipple1 lineStyle0 red red outlineStipple)
|
||||
( display grid1 stipple0 solid gray gray solid )
|
||||
( display Unrouted3 stipple0 lineStyle1 pink pink solid )
|
||||
( display ViaNet x solid magenta magenta outlineStipple)
|
||||
( display select stipple0 solid tan tan solid )
|
||||
( display Poly2Net dots4 lineStyle0 orange orange outlineStipple)
|
||||
( display winText solid solid winText winText solid )
|
||||
( display Unrouted4 stipple0 lineStyle1 orange orange solid )
|
||||
( display wireLbl solid lineStyle0 cyan cyan solid )
|
||||
( display designFlow7 stipple1 lineStyle0 cyan cyan outlineStipple)
|
||||
( display align stipple0 solid tan tan solid )
|
||||
( display Poly2Pin blank solid yellow yellow outline )
|
||||
( display Unrouted5 stipple0 lineStyle1 green green solid )
|
||||
( display unset stipple0 solid forest forest solid )
|
||||
( display Poly1Net dots4 lineStyle0 red red outlineStipple)
|
||||
( display Resistor dots2 lineStyle0 cyan cyan outlineStipple)
|
||||
( display DiodeNet dots4 lineStyle0 cream cream outlineStipple)
|
||||
( display designFlow6 stipple1 lineStyle0 tan tan outlineStipple)
|
||||
( display Unrouted6 stipple0 lineStyle1 blue blue solid )
|
||||
( display resist stipple0 solid cyan cyan solid )
|
||||
( display designFlow5 stipple1 lineStyle0 silver silver outlineStipple)
|
||||
( display CapWellNet brick solid slate slate outlineStipple)
|
||||
( display Unrouted7 stipple0 lineStyle1 purple purple solid )
|
||||
( display CannotoccupyBnd blank solid red red outline )
|
||||
( display winTopShadow solid solid white white solid )
|
||||
( display designFlow4 stipple1 lineStyle0 black black outlineStipple)
|
||||
( display softFence stipple0 solid yellow yellow solid )
|
||||
( display ResistorNet dots4 solid cyan cyan outlineStipple)
|
||||
( display winError solid solid winColor5 winColor5 solid )
|
||||
( display changedLayerTl1 stipple0 solid yellow yellow solid )
|
||||
( display prBoundaryLbl stipple0 solid purple purple solid )
|
||||
( display ActXNet x solid yellow yellow outlineStipple)
|
||||
( display Pbase stipple10 lineStyle0 yellow yellow outlineStipple)
|
||||
( display Active dots2 lineStyle0 yellow yellow outlineStipple)
|
||||
( display changedLayerTl0 stipple0 solid red red solid )
|
||||
( display spike stipple0 solid purple purple solid )
|
||||
( display Metal3 grid solid navy violet outlineStipple)
|
||||
( display text blank solid white white outline )
|
||||
( display Poly1Pin stipple0 lineStyle0 red red solid )
|
||||
( display Row blank solid cyan cyan outline )
|
||||
( display Pwell stipple9 lineStyle0 slate slate outlineStipple)
|
||||
( display Metal2 stipple5 lineStyle0 magenta magenta outlineStipple)
|
||||
( display wire solid lineStyle0 cyan cyan solid )
|
||||
( display ActX solid solid yellow yellow solid )
|
||||
( display Metal1 stipple6 lineStyle0 cadetBlue cadetBlue outlineStipple)
|
||||
( display Cannotoccupy blank solid red red outline )
|
||||
( display GroupLbl stipple0 solid green green solid )
|
||||
( display axis stipple0 solid slate slate solid )
|
||||
( display SiBlockNet x dashed tan tan outlineStipple)
|
||||
( display edgeLayer stipple0 solid gray gray solid )
|
||||
( display annotate2 stipple0 solid lime lime solid )
|
||||
( display Metal1Pin stipple0 lineStyle0 blue blue solid )
|
||||
( display Diode stipple7 lineStyle0 cream cream outlineStipple)
|
||||
( display Glass X lineStyle0 white white X )
|
||||
( display ViaXNet x solid magenta magenta outlineStipple)
|
||||
( display annotate3 stipple0 solid cyan cyan solid )
|
||||
( display Poly2 dots1 lineStyle0 orange orange outlineStipple)
|
||||
( display deviceAnt stipple0 solid yellow yellow solid )
|
||||
( display winBottomShadow solid solid winColor1 winColor1 solid )
|
||||
( display PselectNet dots4 solid brown brown outlineStipple)
|
||||
( display comment stipple0 lineStyle0 winBack winBack solid )
|
||||
( display Poly1 dots lineStyle0 red red outlineStipple)
|
||||
( display Unrouted stipple0 lineStyle1 winColor5 winColor5 solid )
|
||||
( display stretch stipple0 solid yellow yellow solid )
|
||||
( display XP blank lineStyle0 winBack gold outline )
|
||||
( display annotate1 stipple0 solid pink pink solid )
|
||||
( display Group stipple2 solid green green outlineStipple)
|
||||
( display deviceLbl stipple0 solid green green solid )
|
||||
( display annotate6 stipple0 solid silver silver solid )
|
||||
( display GlassNet blank solid yellow yellow outline )
|
||||
( display Canplace blank solid cyan cyan outline )
|
||||
( display annotate7 stipple0 solid red red solid )
|
||||
( display Via2 solid solid navy navy solid )
|
||||
( display Metal2Pin stipple0 lineStyle0 magenta magenta solid )
|
||||
( display annotate4 stipple0 solid yellow yellow solid )
|
||||
( display device1 stipple1 lineStyle0 green green outlineStipple)
|
||||
( display "90" blank solid white white outline )
|
||||
( display markerWarn x solid yellow yellow outlineStipple)
|
||||
( display text2 stipple1 lineStyle0 white white outlineStipple)
|
||||
( display CapacitorNet dots4 lineStyle0 tan tan outlineStipple)
|
||||
( display designFlow stipple1 lineStyle0 green green outlineStipple)
|
||||
( display hilite1 stipple0 solid silver silver solid )
|
||||
( display device blank solid green green outline )
|
||||
( display prBoundary stipple0 solid purple purple solid )
|
||||
( display annotate5 stipple0 solid white white solid )
|
||||
( display text1 stipple0 dashed white white solid )
|
||||
( display Via solid solid magenta magenta solid )
|
||||
( display Capacitor stipple7 lineStyle0 tan tan outlineStipple)
|
||||
( display markerErr x solid white white outlineStipple)
|
||||
( display unknown stipple0 solid yellow yellow solid )
|
||||
( display annotate stipple0 solid orange orange solid )
|
||||
( display P1ConNet x solid red red outlineStipple)
|
||||
( display hilite3 stipple0 solid cyan cyan solid )
|
||||
( display winActiveBanner solid solid winColor3 winColor3 solid )
|
||||
( display pinLbl stipple0 solid red red solid )
|
||||
( display device2 stipple0 lineStyle1 green green solid )
|
||||
( display grid stipple0 solid slate slate solid )
|
||||
( display winBackground solid solid winBack winBack solid )
|
||||
( display Metal1Net dots4 lineStyle0 blue blue outlineStipple)
|
||||
( display hilite2 stipple0 solid tan tan solid )
|
||||
( display annotate8 stipple0 solid tan tan solid )
|
||||
( display hilite5 stipple0 solid lime lime solid )
|
||||
( display annotate9 stipple0 solid green green solid )
|
||||
( display Metal2Net dots4 lineStyle0 magenta magenta outlineStipple)
|
||||
( display Metal3Pin stipple0 solid navy navy solid )
|
||||
( display hilite4 stipple0 solid gray gray solid )
|
||||
( display y0 stipple0 solid gray gray solid )
|
||||
( display supply stipple0 solid lime lime solid )
|
||||
( display ActiveNet dots4 lineStyle0 yellow yellow outlineStipple)
|
||||
( display hilite7 stipple0 solid cream cream solid )
|
||||
( display y1 stipple0 solid brown brown solid )
|
||||
( display defaultPacket x solid chocolate winColor2 outlineStipple)
|
||||
( display Via2Net cross solid navy navy outlineStipple)
|
||||
( display NselectNet dots4 solid green green outlineStipple)
|
||||
( display Unrouted8 stipple0 lineStyle1 gold gold solid )
|
||||
( display hilite6 stipple0 solid orange orange solid )
|
||||
( display y2 stipple0 solid red red solid )
|
||||
( display winBorder solid solid winColor2 winColor2 solid )
|
||||
( display Nwell dats5 thickLine slate slate outlineStipple)
|
||||
( display Unrouted9 stipple0 lineStyle1 silver silver solid )
|
||||
( display hilite9 stipple0 solid pink pink solid )
|
||||
( display SiBlock blank dashed tan tan outline )
|
||||
( display y3 stipple0 solid orange orange solid )
|
||||
( display prBoundaryBnd stipple0 solid cyan cyan solid )
|
||||
( display winForeground solid solid winFore winFore solid )
|
||||
( display hilite8 stipple0 solid magenta magenta solid )
|
||||
( display y4 stipple0 solid yellow yellow solid )
|
||||
( display Pselect dots1 solid brown brown outlineStipple)
|
||||
( display winInactiveBanner solid solid winColor4 winColor4 solid )
|
||||
( display designFlow9 stipple1 lineStyle0 orange orange outlineStipple)
|
||||
( display winButton solid solid winFore winFore solid )
|
||||
( display y5 stipple0 solid green green solid )
|
||||
( display hiz stipple0 solid orange orange solid )
|
||||
( display drive stipple0 solid blue blue solid )
|
||||
( display wireFlt stipple0 dashed red red solid )
|
||||
( display instanceLbl stipple0 solid gold gold solid )
|
||||
( display P2ConNet x lineStyle0 orange orange outlineStipple)
|
||||
( display designFlow8 stipple1 lineStyle0 navy navy outlineStipple)
|
||||
( display y6 stipple0 solid blue blue solid )
|
||||
( display PwellNet dots4 lineStyle0 slate slate outlineStipple)
|
||||
( display P1Con solid solid red red solid )
|
||||
( display CapWell dagger solid slate slate outlineStipple)
|
||||
( display y7 stipple0 solid purple purple solid )
|
||||
( display ViaX solid solid magenta magenta solid )
|
||||
( display HR x solid chocolate winColor2 outlineStipple)
|
||||
( display HRnet x solid chocolate winColor2 outlineStipple)
|
||||
)
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
import os
|
||||
CWD = os.environ.get("OPENRAM_TECH") + "/scn3me_subm/tf"
|
||||
ui().importCds("default", CWD+"/display.drf", CWD+"/mosis.tf", 1000, 1, CWD+"/layers.map")
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
Pwell drawing 41 0
|
||||
Nwell drawing 42 0
|
||||
Active drawing 43 0
|
||||
Poly1 drawing 46 0
|
||||
Pselect drawing 45 0
|
||||
Nselect drawing 44 0
|
||||
contact drawing 25 0
|
||||
P1Con drawing 47 0
|
||||
ActX drawing 48 0
|
||||
Metal1 drawing 49 0
|
||||
Via drawing 50 0
|
||||
Metal2 drawing 51 0
|
||||
Via2 drawing 61 0
|
||||
Metal3 drawing 62 0
|
||||
Glass drawing 52 0
|
||||
text drawing 83 0
|
||||
|
|
@ -0,0 +1,848 @@
|
|||
; Generated on Sep 28 16:05:23 1998
|
||||
; with @(#)$CDS: icfb.exe version 4.4.1 06/17/98 23:40 (cds10067) $
|
||||
;
|
||||
; Matt Clapp fixed: October 10, 2002
|
||||
; added via devices, deleted useless app-specific crap,
|
||||
; added lxExtractRules so undo in layout editor doesn't
|
||||
; complain.
|
||||
|
||||
|
||||
;********************************
|
||||
; LAYER DEFINITION
|
||||
;********************************
|
||||
|
||||
layerDefinitions(
|
||||
techLayers(
|
||||
;( LayerName Layer# Abbreviation )
|
||||
;( --------- ------ ------------ )
|
||||
;User-Defined Layers:
|
||||
( P2Con 3 P2Con )
|
||||
( Poly2 7 Poly2 )
|
||||
( Pbase 10 Pbase )
|
||||
( Resistor 16 Resisto )
|
||||
( Capacitor 17 Capacit )
|
||||
( Diode 18 Diode )
|
||||
( SiBlock 29 SiBlock )
|
||||
( HR 34 HR )
|
||||
( Pwell 41 Pwell )
|
||||
( Nwell 42 Nwell )
|
||||
( Active 43 Active )
|
||||
( Pselect 44 Pselect )
|
||||
( Nselect 45 Nselect )
|
||||
( Poly1 46 Poly1 )
|
||||
( P1Con 47 P1Con )
|
||||
( ActX 48 ActX )
|
||||
( Metal1 49 Metal1 )
|
||||
( Via 50 Via )
|
||||
( Metal2 51 Metal2 )
|
||||
( Glass 52 Glass )
|
||||
( CapWell 59 CapWell )
|
||||
( XP 60 XP )
|
||||
( Via2 61 Via2 )
|
||||
( Metal3 62 Metal3 )
|
||||
( A1 80 A1 )
|
||||
( A2 81 A2 )
|
||||
( comment 117 comment )
|
||||
;System-Reserved Layers:
|
||||
( Unrouted 200 Unroute )
|
||||
( Row 201 Row )
|
||||
( Group 202 Group )
|
||||
( Cannotoccupy 203 Cannoto )
|
||||
( Canplace 204 Canplac )
|
||||
( hardFence 205 hardFen )
|
||||
( softFence 206 softFen )
|
||||
( y0 207 y0 )
|
||||
( y1 208 y1 )
|
||||
( y2 209 y2 )
|
||||
( y3 210 y3 )
|
||||
( y4 211 y4 )
|
||||
( y5 212 y5 )
|
||||
( y6 213 y6 )
|
||||
( y7 214 y7 )
|
||||
( y8 215 y8 )
|
||||
( y9 216 y9 )
|
||||
( designFlow 217 designF )
|
||||
( stretch 218 stretch )
|
||||
( edgeLayer 219 edgeLay )
|
||||
( changedLayer 220 changed )
|
||||
( unset 221 unset )
|
||||
( unknown 222 unknown )
|
||||
( spike 223 spike )
|
||||
( hiz 224 hiz )
|
||||
( resist 225 resist )
|
||||
( drive 226 drive )
|
||||
( supply 227 supply )
|
||||
( wire 228 wire )
|
||||
( pin 229 pin )
|
||||
( text 230 text )
|
||||
( device 231 device )
|
||||
( border 232 border )
|
||||
( snap 233 snap )
|
||||
( align 234 align )
|
||||
( prBoundary 235 prBound )
|
||||
( instance 236 instanc )
|
||||
( annotate 237 annotat )
|
||||
( marker 238 marker )
|
||||
( select 239 select )
|
||||
( grid 251 grid )
|
||||
( axis 252 axis )
|
||||
( hilite 253 hilite )
|
||||
( background 254 backgro )
|
||||
) ;techLayers
|
||||
|
||||
techPurposes(
|
||||
;( PurposeName Purpose# Abbreviation )
|
||||
;( ----------- -------- ------------ )
|
||||
;User-Defined Purposes:
|
||||
;System-Reserved Purposes:
|
||||
( warning 234 wng )
|
||||
( tool1 235 tl1 )
|
||||
( tool0 236 tl0 )
|
||||
( label 237 lbl )
|
||||
( flight 238 flt )
|
||||
( error 239 err )
|
||||
( annotate 240 ant )
|
||||
( drawing1 241 dr1 )
|
||||
( drawing2 242 dr2 )
|
||||
( drawing3 243 dr3 )
|
||||
( drawing4 244 dr4 )
|
||||
( drawing5 245 dr5 )
|
||||
( drawing6 246 dr6 )
|
||||
( drawing7 247 dr7 )
|
||||
( drawing8 248 dr8 )
|
||||
( drawing9 249 dr9 )
|
||||
( boundary 250 bnd )
|
||||
( pin 251 pin )
|
||||
( drawing 252 drw )
|
||||
( net 253 net )
|
||||
( cell 254 cel )
|
||||
( all 255 all )
|
||||
) ;techPurposes
|
||||
|
||||
techLayerPurposePriorities(
|
||||
;layers are ordered from lowest to highest priority
|
||||
; (higher priority is drawn on top of lower priority)
|
||||
;( LayerName Purpose )
|
||||
;( --------- ------- )
|
||||
( background drawing )
|
||||
( grid drawing )
|
||||
( grid drawing1 )
|
||||
( Nwell drawing )
|
||||
( Pwell drawing )
|
||||
( CapWell drawing )
|
||||
( Pselect drawing )
|
||||
( Nselect drawing )
|
||||
( Active drawing )
|
||||
( ActX drawing )
|
||||
( SiBlock drawing )
|
||||
( HR drawing )
|
||||
( Poly1 drawing )
|
||||
( P1Con drawing )
|
||||
( Poly2 drawing )
|
||||
( P2Con drawing )
|
||||
( Metal1 drawing )
|
||||
( Via drawing )
|
||||
( Metal2 drawing )
|
||||
( Via2 drawing )
|
||||
( Metal3 drawing )
|
||||
( annotate drawing )
|
||||
( annotate drawing1 )
|
||||
( annotate drawing2 )
|
||||
( annotate drawing3 )
|
||||
( annotate drawing4 )
|
||||
( annotate drawing5 )
|
||||
( annotate drawing6 )
|
||||
( annotate drawing7 )
|
||||
( annotate drawing8 )
|
||||
( annotate drawing9 )
|
||||
( Poly1 pin )
|
||||
( Metal1 pin )
|
||||
( Metal2 pin )
|
||||
( Metal3 pin )
|
||||
( Glass drawing )
|
||||
( XP drawing )
|
||||
( prBoundary drawing )
|
||||
( prBoundary boundary )
|
||||
( instance drawing )
|
||||
( prBoundary label )
|
||||
( instance label )
|
||||
( Row drawing )
|
||||
( Nwell net )
|
||||
( align drawing )
|
||||
( Pwell net )
|
||||
( CapWell net )
|
||||
( hardFence drawing )
|
||||
( Active net )
|
||||
( softFence drawing )
|
||||
( Row label )
|
||||
( Group drawing )
|
||||
( Group label )
|
||||
( Cannotoccupy drawing )
|
||||
( Cannotoccupy boundary )
|
||||
( Canplace drawing )
|
||||
( ActX net )
|
||||
( A2 drawing )
|
||||
( A1 drawing )
|
||||
( comment drawing )
|
||||
( border drawing )
|
||||
( Pselect net )
|
||||
( Nselect net )
|
||||
( SiBlock net )
|
||||
( HR net )
|
||||
( wire drawing )
|
||||
( Poly1 net )
|
||||
( wire label )
|
||||
( P1Con net )
|
||||
( wire flight )
|
||||
( Metal1 net )
|
||||
( device annotate )
|
||||
( Metal2 net )
|
||||
( device label )
|
||||
( Via net )
|
||||
( Metal3 net )
|
||||
( Via2 net )
|
||||
( pin label )
|
||||
( text drawing )
|
||||
( pin drawing )
|
||||
( text drawing1 )
|
||||
( pin annotate )
|
||||
( device drawing )
|
||||
( axis drawing )
|
||||
( edgeLayer drawing )
|
||||
( edgeLayer pin )
|
||||
( snap drawing )
|
||||
( stretch drawing )
|
||||
( y0 drawing )
|
||||
( y1 drawing )
|
||||
( y2 drawing )
|
||||
( y3 drawing )
|
||||
( y4 drawing )
|
||||
( y5 drawing )
|
||||
( y6 drawing )
|
||||
( y7 drawing )
|
||||
( y8 drawing )
|
||||
( y9 drawing )
|
||||
( hilite drawing )
|
||||
( hilite drawing1 )
|
||||
( hilite drawing2 )
|
||||
( hilite drawing3 )
|
||||
( hilite drawing4 )
|
||||
( hilite drawing5 )
|
||||
( hilite drawing6 )
|
||||
( hilite drawing7 )
|
||||
( hilite drawing8 )
|
||||
( hilite drawing9 )
|
||||
( select drawing )
|
||||
( drive drawing )
|
||||
( hiz drawing )
|
||||
( resist drawing )
|
||||
( spike drawing )
|
||||
( supply drawing )
|
||||
( unknown drawing )
|
||||
( unset drawing )
|
||||
( designFlow drawing )
|
||||
( designFlow drawing1 )
|
||||
( designFlow drawing2 )
|
||||
( designFlow drawing3 )
|
||||
( designFlow drawing4 )
|
||||
( designFlow drawing5 )
|
||||
( designFlow drawing6 )
|
||||
( designFlow drawing7 )
|
||||
( designFlow drawing8 )
|
||||
( designFlow drawing9 )
|
||||
( changedLayer tool0 )
|
||||
( changedLayer tool1 )
|
||||
( marker warning )
|
||||
( marker error )
|
||||
( device drawing1 )
|
||||
( Pbase drawing )
|
||||
( Pbase net )
|
||||
( Resistor net )
|
||||
( Resistor drawing )
|
||||
( Capacitor net )
|
||||
( Capacitor drawing )
|
||||
( Diode net )
|
||||
( Diode drawing )
|
||||
( Poly2 net )
|
||||
( P2Con net )
|
||||
( device drawing2 )
|
||||
( Unrouted drawing )
|
||||
( text drawing2 )
|
||||
( Unrouted drawing1 )
|
||||
( Unrouted drawing2 )
|
||||
( Unrouted drawing3 )
|
||||
( Unrouted drawing4 )
|
||||
( Unrouted drawing5 )
|
||||
( Unrouted drawing6 )
|
||||
( Unrouted drawing7 )
|
||||
( Unrouted drawing8 )
|
||||
( Unrouted drawing9 )
|
||||
) ;techLayerPurposePriorities
|
||||
|
||||
techDisplays(
|
||||
;( LayerName Purpose Packet Vis Sel Con2ChgLy DrgEnbl Valid )
|
||||
;( --------- ------- ------ --- --- --------- ------- ----- )
|
||||
( background drawing background t nil nil nil nil )
|
||||
( grid drawing grid t nil nil nil nil )
|
||||
( grid drawing1 grid1 t nil nil nil nil )
|
||||
( Nwell drawing Nwell t t t t t )
|
||||
( Pwell drawing Pwell t t t t nil )
|
||||
( Active drawing Active t t t t t )
|
||||
( ActX drawing ActX t t t t t )
|
||||
( Pselect drawing Pselect t t t t t )
|
||||
( Nselect drawing Nselect t t t t t )
|
||||
( SiBlock drawing SiBlock t t t t t )
|
||||
( HR drawing HR t t t t t )
|
||||
( CapWell drawing CapWell t t t t t )
|
||||
( Poly1 drawing Poly1 t t t t t )
|
||||
( P1Con drawing P1Con t t t t t )
|
||||
( Metal1 drawing Metal1 t t t t t )
|
||||
( Via drawing Via t t t t t )
|
||||
( Metal2 drawing Metal2 t t t t t )
|
||||
( annotate drawing annotate t t nil t nil )
|
||||
( annotate drawing1 annotate1 t t nil t nil )
|
||||
( annotate drawing2 annotate2 t t nil t nil )
|
||||
( annotate drawing3 annotate3 t t nil t nil )
|
||||
( annotate drawing4 annotate4 t t nil t nil )
|
||||
( annotate drawing5 annotate5 t t nil t nil )
|
||||
( annotate drawing6 annotate6 t t nil t nil )
|
||||
( annotate drawing7 annotate7 t t nil t nil )
|
||||
( annotate drawing8 annotate8 t t nil t nil )
|
||||
( annotate drawing9 annotate9 t t nil t nil )
|
||||
( Via2 drawing Via2 t t t t t )
|
||||
( Metal3 drawing Metal3 t t t t t )
|
||||
( Glass drawing Glass t t t nil t )
|
||||
( XP drawing XP t t t nil t )
|
||||
( Metal1 pin Metal1Pin t t t nil t )
|
||||
( Metal2 pin Metal2Pin t t t nil t )
|
||||
( Metal3 pin Metal3Pin t t t nil t )
|
||||
( Poly1 pin Poly1Pin t t t nil t )
|
||||
( prBoundary drawing prBoundary t t nil t nil )
|
||||
( prBoundary boundary prBoundaryBnd t t nil t nil )
|
||||
( instance drawing instance t t nil t t )
|
||||
( prBoundary label prBoundaryLbl t t t t nil )
|
||||
( instance label instanceLbl t t t t nil )
|
||||
( Row drawing Row t t t t nil )
|
||||
( Nwell net NwellNet t t t nil nil )
|
||||
( align drawing align t t nil t nil )
|
||||
( Pwell net PwellNet t t t nil nil )
|
||||
( CapWell net CapWellNet t t t nil nil )
|
||||
( SiBlock net SiBlockNet t t t nil nil )
|
||||
( HR net HRnet t t t nil nil )
|
||||
( hardFence drawing hardFence t t t t nil )
|
||||
( Active net ActiveNet t t t nil nil )
|
||||
( softFence drawing softFence t t t t nil )
|
||||
( Row label RowLbl t t t t nil )
|
||||
( Group drawing Group t t t t nil )
|
||||
( Group label GroupLbl t t t t nil )
|
||||
( Cannotoccupy drawing Cannotoccupy t t t t nil )
|
||||
( Cannotoccupy boundary CannotoccupyBnd t t t t nil )
|
||||
( Canplace drawing Canplace t t t t nil )
|
||||
( ActX net ActXNet t t t nil nil )
|
||||
( A2 drawing A2 t t t t nil )
|
||||
( A1 drawing A1 t t t t nil )
|
||||
( comment drawing comment t t t t nil )
|
||||
( border drawing border t t t t nil )
|
||||
( Pselect net PselectNet t t t nil nil )
|
||||
( Nselect net NselectNet t t t nil nil )
|
||||
( wire drawing wire t t t t nil )
|
||||
( Poly1 net Poly1Net t t t nil nil )
|
||||
( wire label wireLbl t t t t nil )
|
||||
( P1Con net P1ConNet t t t nil nil )
|
||||
( wire flight wireFlt t t t t nil )
|
||||
( Metal1 net Metal1Net t t t nil nil )
|
||||
( device annotate deviceAnt t t t t nil )
|
||||
( Metal2 net Metal2Net t t t nil nil )
|
||||
( Metal3 net Metal3Net t t t nil nil )
|
||||
( device label deviceLbl t t t t nil )
|
||||
( Via net ViaNet t t t nil nil )
|
||||
( Via2 net Via2Net t t t nil nil )
|
||||
( pin label pinLbl t t t t nil )
|
||||
( text drawing text t t t t t )
|
||||
( pin drawing pin t t t t nil )
|
||||
( text drawing1 text1 t t t t nil )
|
||||
( pin annotate pinAnt t t t t nil )
|
||||
( device drawing device t t t t nil )
|
||||
( axis drawing axis t t t t nil )
|
||||
( edgeLayer drawing edgeLayer t t nil t nil )
|
||||
( edgeLayer pin edgeLayerPin t t nil t nil )
|
||||
( snap drawing snap t t nil t nil )
|
||||
( stretch drawing stretch t t nil t nil )
|
||||
( y0 drawing y0 t t nil t nil )
|
||||
( y1 drawing y1 t t nil t nil )
|
||||
( y2 drawing y2 t t nil t nil )
|
||||
( y3 drawing y3 t t nil t nil )
|
||||
( y4 drawing y4 t t nil t nil )
|
||||
( y5 drawing y5 t t nil t nil )
|
||||
( y6 drawing y6 t t nil t nil )
|
||||
( y7 drawing y7 t t nil t nil )
|
||||
( y8 drawing y8 t t nil t nil )
|
||||
( y9 drawing y9 t t nil t nil )
|
||||
( hilite drawing hilite t t nil t nil )
|
||||
( hilite drawing1 hilite1 t t t t nil )
|
||||
( hilite drawing2 hilite2 t t nil t nil )
|
||||
( hilite drawing3 hilite3 t t t t nil )
|
||||
( hilite drawing4 hilite4 t t t t nil )
|
||||
( hilite drawing5 hilite5 t t t t nil )
|
||||
( hilite drawing6 hilite6 t t t t nil )
|
||||
( hilite drawing7 hilite7 t t t t nil )
|
||||
( hilite drawing8 hilite8 t t t t nil )
|
||||
( hilite drawing9 hilite9 t t t t nil )
|
||||
( select drawing select t t nil t nil )
|
||||
( drive drawing drive t t t t nil )
|
||||
( hiz drawing hiz t t t t nil )
|
||||
( resist drawing resist t t t t nil )
|
||||
( spike drawing spike t t t t nil )
|
||||
( supply drawing supply t t t t nil )
|
||||
( unknown drawing unknown t t t t nil )
|
||||
( unset drawing unset t t t t nil )
|
||||
( designFlow drawing designFlow t t t nil nil )
|
||||
( designFlow drawing1 designFlow1 t t t nil nil )
|
||||
( designFlow drawing2 designFlow2 t t t nil nil )
|
||||
( designFlow drawing3 designFlow3 t t t nil nil )
|
||||
( designFlow drawing4 designFlow4 t t t nil nil )
|
||||
( designFlow drawing5 designFlow5 t t t nil nil )
|
||||
( designFlow drawing6 designFlow6 t t t nil nil )
|
||||
( designFlow drawing7 designFlow7 t t t nil nil )
|
||||
( designFlow drawing8 designFlow8 t t t nil nil )
|
||||
( designFlow drawing9 designFlow9 t t t nil nil )
|
||||
( changedLayer tool0 changedLayerTl0 nil nil nil nil nil )
|
||||
( changedLayer tool1 changedLayerTl1 nil nil t nil nil )
|
||||
( marker warning markerWarn t t t t nil )
|
||||
( marker error markerErr t t t t nil )
|
||||
( device drawing1 device1 t t t t nil )
|
||||
( Poly2 net Poly2Net t t t nil nil )
|
||||
( Poly2 drawing Poly2 t t t t t )
|
||||
( P2Con net P2ConNet t t t nil nil )
|
||||
( P2Con drawing P2Con t t t t t )
|
||||
( Pbase net PbaseNet t t t nil nil )
|
||||
( Pbase drawing Pbase t t t t t )
|
||||
( Resistor net ResistorNet t t t nil nil )
|
||||
( Resistor drawing Resistor t t t t t )
|
||||
( Capacitor net CapacitorNet t t t nil nil )
|
||||
( Capacitor drawing Capacitor t t t t t )
|
||||
( Diode net DiodeNet t t t nil nil )
|
||||
( Diode drawing Diode t t t t t )
|
||||
( device drawing2 device2 t t t t nil )
|
||||
( Unrouted drawing Unrouted t t t t nil )
|
||||
( text drawing2 text2 t t t t nil )
|
||||
( Unrouted drawing1 Unrouted1 t t t t nil )
|
||||
( Unrouted drawing2 Unrouted2 t t t t nil )
|
||||
( Unrouted drawing3 Unrouted3 t t t t nil )
|
||||
( Unrouted drawing4 Unrouted4 t t t t nil )
|
||||
( Unrouted drawing5 Unrouted5 t t t t nil )
|
||||
( Unrouted drawing6 Unrouted6 t t t t nil )
|
||||
( Unrouted drawing7 Unrouted7 t t t t nil )
|
||||
( Unrouted drawing8 Unrouted8 t t t t nil )
|
||||
( Unrouted drawing9 Unrouted9 t t t t nil )
|
||||
) ;techDisplays
|
||||
|
||||
; I don't think the following is necessary (or used!)
|
||||
techLayerProperties(
|
||||
;( PropName Layer1 [ Layer2 ] PropValue )
|
||||
( contactLimit P2Con 10000 )
|
||||
( eqPinLimit P2Con 10000 )
|
||||
( horizontalJogLength P2Con 2147483648.000000 )
|
||||
( routingGrid P2Con 1.000000 )
|
||||
( verticalJogLength P2Con 2147483648.000000 )
|
||||
( routingGrid Poly2 1.000000 )
|
||||
( contactLimit Active 10000 )
|
||||
( eqPinLimit Active 10000 )
|
||||
( horizontalJogLength Active 2147483648.000000 )
|
||||
( routingGrid Active 1.000000 )
|
||||
( verticalJogLength Active 2147483648.000000 )
|
||||
( routingGrid Poly1 1.000000 )
|
||||
( contactLimit P1Con 10000 )
|
||||
( eqPinLimit P1Con 10000 )
|
||||
( horizontalJogLength P1Con 2147483648.000000 )
|
||||
( routingGrid P1Con 1.000000 )
|
||||
( verticalJogLength P1Con 2147483648.000000 )
|
||||
( contactLimit ActX 10000 )
|
||||
( eqPinLimit ActX 10000 )
|
||||
( horizontalJogLength ActX 2147483648.000000 )
|
||||
( routingGrid ActX 1.000000 )
|
||||
( verticalJogLength ActX 2147483648.000000 )
|
||||
( routingGrid Metal1 1.000000 )
|
||||
( contactLimit Via 10000 )
|
||||
( eqPinLimit Via 10000 )
|
||||
( horizontalJogLength Via 2147483648.000000 )
|
||||
( routingGrid Via 1.000000 )
|
||||
( verticalJogLength Via 2147483648.000000 )
|
||||
( routingGrid Metal2 1.000000 )
|
||||
)
|
||||
|
||||
) ;layerDefinitions
|
||||
|
||||
|
||||
;********************************
|
||||
; DEVICE RULES
|
||||
;********************************
|
||||
|
||||
devices(
|
||||
tcCreateCDSDeviceClass()
|
||||
|
||||
symContactDevice(
|
||||
;( deviceName viaLayer viaPurpose
|
||||
( VIA Via drawing
|
||||
|
||||
; layer1 purpose1 [implant1]
|
||||
Metal1 drawing
|
||||
|
||||
; layer2 purpose2 [implant2]
|
||||
Metal2 drawing
|
||||
|
||||
; width length [( row column xPitch yPitch xBias yBias )]
|
||||
; 2 2 ( 1 1 _NA_ _NA_ _NA_ _NA_ )
|
||||
2 2
|
||||
|
||||
; encLayer1 encLayer2 legalRegion )
|
||||
1 1 _NA_)
|
||||
) ;symContactDevice
|
||||
|
||||
symContactDevice(
|
||||
;( deviceName viaLayer viaPurpose
|
||||
( VIA2 Via2 drawing
|
||||
|
||||
; layer1 purpose1 [implant1]
|
||||
Metal2 drawing
|
||||
|
||||
; layer2 purpose2 [implant2]
|
||||
Metal3 drawing
|
||||
|
||||
; width length [( row column xPitch yPitch xBias yBias )]
|
||||
; 2 2 ( 1 1 _NA_ _NA_ _NA_ _NA_ )
|
||||
2 2
|
||||
|
||||
; encLayer1 encLayer2 legalRegion )
|
||||
1 2 _NA_)
|
||||
) ;symContactDevice
|
||||
|
||||
) ;devices
|
||||
|
||||
|
||||
;********************************
|
||||
; LAYER RULES
|
||||
;********************************
|
||||
|
||||
layerRules(
|
||||
streamLayers(
|
||||
;( layer streamNumber dataType translate )
|
||||
;( ----- ------------ -------- --------- )
|
||||
( ("background" "drawing") 0 0 nil )
|
||||
( ("grid" "drawing") 0 0 nil )
|
||||
( ("grid" "drawing1") 0 0 nil )
|
||||
( ("Nwell" "drawing") 42 0 t )
|
||||
( ("Pwell" "drawing") 41 0 t )
|
||||
( ("Active" "drawing") 43 0 t )
|
||||
( ("ActX" "drawing") 48 0 t )
|
||||
( ("Pselect" "drawing") 44 0 t )
|
||||
( ("Nselect" "drawing") 45 0 t )
|
||||
( ("Poly1" "drawing") 46 0 t )
|
||||
( ("P1Con" "drawing") 47 0 t )
|
||||
( ("Metal1" "drawing") 49 0 t )
|
||||
( ("Metal2" "drawing") 51 0 t )
|
||||
( ("annotate" "drawing") 0 0 nil )
|
||||
( ("annotate" "drawing1") 0 0 nil )
|
||||
( ("annotate" "drawing2") 0 0 nil )
|
||||
( ("annotate" "drawing3") 0 0 nil )
|
||||
( ("annotate" "drawing4") 0 0 nil )
|
||||
( ("annotate" "drawing5") 0 0 nil )
|
||||
( ("annotate" "drawing6") 0 0 nil )
|
||||
( ("annotate" "drawing7") 0 0 nil )
|
||||
( ("annotate" "drawing8") 0 0 nil )
|
||||
( ("annotate" "drawing9") 0 0 nil )
|
||||
( ("Via" "drawing") 50 0 t )
|
||||
( ("Glass" "drawing") 52 0 t )
|
||||
( ("XP" "drawing") 60 0 t )
|
||||
( ("Metal2" "pin") 0 0 nil )
|
||||
( ("Poly1" "pin") 0 0 nil )
|
||||
( ("prBoundary" "drawing") 0 0 nil )
|
||||
( ("Metal1" "pin") 0 0 nil )
|
||||
( ("prBoundary" "boundary") 0 0 nil )
|
||||
( ("instance" "drawing") 246 0 nil )
|
||||
( ("instance" "label") 0 0 nil )
|
||||
( ("Nwell" "net") 0 0 nil )
|
||||
( ("align" "drawing") 0 0 nil )
|
||||
( ("Pwell" "net") 0 0 nil )
|
||||
( ("hardFence" "drawing") 0 0 nil )
|
||||
( ("Active" "net") 0 0 nil )
|
||||
( ("softFence" "drawing") 0 0 nil )
|
||||
( ("ActX" "net") 0 0 nil )
|
||||
( ("A2" "drawing") 5 0 nil )
|
||||
( ("A1" "drawing") 2 0 nil )
|
||||
( ("comment" "drawing") 0 0 nil )
|
||||
( ("border" "drawing") 0 0 nil )
|
||||
( ("Pselect" "net") 0 0 nil )
|
||||
( ("Nselect" "net") 0 0 nil )
|
||||
( ("wire" "drawing") 0 0 nil )
|
||||
( ("Poly1" "net") 0 0 nil )
|
||||
( ("P1Con" "net") 0 0 nil )
|
||||
( ("Metal1" "net") 0 0 nil )
|
||||
( ("Metal2" "net") 0 0 nil )
|
||||
( ("device" "label") 0 0 nil )
|
||||
( ("Via" "net") 0 0 nil )
|
||||
( ("pin" "label") 0 0 nil )
|
||||
( ("text" "drawing") 63 0 t )
|
||||
( ("pin" "drawing") 0 0 nil )
|
||||
( ("device" "drawing") 0 0 nil )
|
||||
( ("axis" "drawing") 0 0 nil )
|
||||
( ("edgeLayer" "drawing") 0 0 nil )
|
||||
( ("edgeLayer" "pin") 0 0 nil )
|
||||
( ("snap" "drawing") 0 0 nil )
|
||||
( ("stretch" "drawing") 0 0 nil )
|
||||
( ("y0" "drawing") 0 0 nil )
|
||||
( ("y1" "drawing") 0 0 nil )
|
||||
( ("y2" "drawing") 0 0 nil )
|
||||
( ("y3" "drawing") 0 0 nil )
|
||||
( ("y4" "drawing") 0 0 nil )
|
||||
( ("y5" "drawing") 0 0 nil )
|
||||
( ("y6" "drawing") 0 0 nil )
|
||||
( ("y7" "drawing") 0 0 nil )
|
||||
( ("y8" "drawing") 0 0 nil )
|
||||
( ("y9" "drawing") 0 0 nil )
|
||||
( ("hilite" "drawing") 0 0 nil )
|
||||
( ("hilite" "drawing2") 0 0 nil )
|
||||
( ("select" "drawing") 0 0 nil )
|
||||
( ("drive" "drawing") 0 0 nil )
|
||||
( ("hiz" "drawing") 0 0 nil )
|
||||
( ("resist" "drawing") 0 0 nil )
|
||||
( ("spike" "drawing") 0 0 nil )
|
||||
( ("supply" "drawing") 0 0 nil )
|
||||
( ("unknown" "drawing") 0 0 nil )
|
||||
( ("unset" "drawing") 0 0 nil )
|
||||
( ("changedLayer" "tool0") 0 0 nil )
|
||||
( ("Resistor" "net") 0 0 nil )
|
||||
( ("Resistor" "drawing") 0 0 nil )
|
||||
( ("Capacitor" "net") 0 0 nil )
|
||||
( ("Capacitor" "drawing") 0 0 nil )
|
||||
( ("Diode" "net") 0 0 nil )
|
||||
( ("Diode" "drawing") 0 0 nil )
|
||||
( ("Poly2" "net") 0 0 nil )
|
||||
( ("Poly2" "drawing") 0 0 nil )
|
||||
( ("P2Con" "net") 0 0 nil )
|
||||
( ("P2Con" "drawing") 0 0 nil )
|
||||
( ("Pbase" "drawing") 0 0 nil )
|
||||
( ("Pbase" "net") 0 0 nil )
|
||||
( P2Con 0 0 nil )
|
||||
( Poly2 0 0 nil )
|
||||
( Pwell 0 0 nil )
|
||||
( Nwell 0 0 nil )
|
||||
( Active 0 0 nil )
|
||||
( Pselect 0 0 nil )
|
||||
( Nselect 0 0 nil )
|
||||
( Poly1 0 0 nil )
|
||||
( P1Con 0 0 nil )
|
||||
( ActX 0 0 nil )
|
||||
( Metal1 0 0 nil )
|
||||
( Via 0 0 nil )
|
||||
( Metal2 0 0 nil )
|
||||
( Glass 0 0 nil )
|
||||
( XP 0 0 nil )
|
||||
( ("Via2" "drawing") 50 0 t )
|
||||
( ("Via2" "net") 0 0 nil )
|
||||
( ("Metal3" "drawing") 50 0 t )
|
||||
( ("Metal3" "net") 0 0 nil )
|
||||
( ("Metal3" "pin") 0 0 nil )
|
||||
( ("CapWell" "drawing") 0 0 nil )
|
||||
( ("CapWell" "net") 0 0 nil )
|
||||
( ("SiBlock" "drawing") 0 0 nil )
|
||||
( ("SiBlock" "net") 0 0 nil )
|
||||
( ("HR" "drawing") 0 0 nil )
|
||||
( ("HR" "net") 0 0 nil )
|
||||
) ;streamLayers
|
||||
|
||||
viaLayers(
|
||||
;( layer1 viaLayer layer2 )
|
||||
;( ------ -------- ------ )
|
||||
( Metal2 Via2 Metal3 )
|
||||
( Metal1 Via Metal2 )
|
||||
( Active ActX Poly1 )
|
||||
( Poly1 P1Con Metal1 )
|
||||
( Poly2 P2Con Metal1 )
|
||||
) ;viaLayers
|
||||
|
||||
) ;layerRules
|
||||
|
||||
|
||||
;********************************
|
||||
; PHYSICAL RULES
|
||||
;********************************
|
||||
|
||||
physicalRules(
|
||||
orderedSpacingRules(
|
||||
;( rule layer1 layer2 value )
|
||||
;( ---- ------ ------ ----- )
|
||||
( minEnclosure "prBoundary" "Metal1" 0.0 )
|
||||
( minEnclosure "Metal2" "Via" 1.0 )
|
||||
( minEnclosure "Metal1" "Via" 1.0 )
|
||||
( minEnclosure "Metal1" "P1Con" 1.0 )
|
||||
( minEnclosure "Metal1" "ActX" 1.0 )
|
||||
( minEnclosure "Nselect" "Active" 2.0 )
|
||||
( minEnclosure "Pselect" "Active" 2.0 )
|
||||
( minEnclosure "Active" "ActX" 1.0 )
|
||||
( minEnclosure "Pwell" "Active" 5.0 )
|
||||
( minEnclosure "Nwell" "Active" 5.0 )
|
||||
) ;orderedSpacingRules
|
||||
|
||||
spacingRules(
|
||||
;( rule layer1 layer2 value )
|
||||
;( ---- ------ ------ ----- )
|
||||
( minSpacing "P2Con" 2.0 )
|
||||
( minSpacing "Poly2" 3.0 )
|
||||
( minSpacing "Pwell" 9.0 )
|
||||
( minSpacing "Nwell" 9.0 )
|
||||
( minSpacing "Active" 3.0 )
|
||||
( minSpacing "Pselect" 2.0 )
|
||||
( minSpacing "Nselect" 2.0 )
|
||||
( minSpacing "Poly1" 2.0 )
|
||||
( minSpacing "P1Con" 2.0 )
|
||||
( minSpacing "ActX" 2.0 )
|
||||
( minSpacing "Metal1" 3.0 )
|
||||
( minSpacing "Via" 3.0 )
|
||||
( minSpacing "Via2" 3.0 )
|
||||
( minSpacing "Metal2" 3.0 )
|
||||
( minSpacing "Metal3" 4.0 )
|
||||
( minSpacing "Glass" 75.0 )
|
||||
( minSpacing "XP" 100.0 )
|
||||
( minSpacing "Metal2" 4.0 )
|
||||
( minSpacing "P1Con" "Via" 2.0 )
|
||||
( minSpacing "ActX" "Via" 2.0 )
|
||||
( minSpacing "ActX" "P2Con" 2.0 )
|
||||
( minSpacing "Poly2" "P2Con" 4.0 )
|
||||
( minSpacing "Poly1" "P1Con" 4.0 )
|
||||
( minSpacing "ActX" "P1Con" 2.0 )
|
||||
( minSpacing "Active" "P1Con" 2.0 )
|
||||
( minSpacing "Active" "Poly2" 2.0 )
|
||||
( minSpacing "Poly1" "Poly2" 2.0 )
|
||||
( minSpacing "Active" "Poly1" 2.0 )
|
||||
( minSpacing "ActX" "Poly1" 2.0 )
|
||||
( minSpacing "Pselect" "Nselect" 0.0 )
|
||||
( minSpacing "Nwell" "Pwell" 9.0 )
|
||||
( minWidth "P2Con" 2.0 )
|
||||
( minWidth "Poly2" 3.0 )
|
||||
( minWidth "Pwell" 10.0 )
|
||||
( minWidth "Nwell" 10.0 )
|
||||
( minWidth "Active" 3.0 )
|
||||
( minWidth "Pselect" 2.0 )
|
||||
( minWidth "Nselect" 2.0 )
|
||||
( minWidth "Poly1" 2.0 )
|
||||
( minWidth "P1Con" 2.0 )
|
||||
( minWidth "ActX" 2.0 )
|
||||
( minWidth "Metal1" 4.0 )
|
||||
( minWidth "Via" 2.0 )
|
||||
( minWidth "Metal2" 4.0 )
|
||||
( minWidth "Glass" 75.0 )
|
||||
( minWidth "XP" 100.0 )
|
||||
( minWidth "Metal3" 6.0 )
|
||||
) ;spacingRules
|
||||
|
||||
mfgGridResolution(
|
||||
( 1.000000 )
|
||||
) ;mfgGridResolution
|
||||
|
||||
) ;physicalRules
|
||||
|
||||
|
||||
;********************************
|
||||
; ELECTRICAL RULES
|
||||
;********************************
|
||||
|
||||
electricalRules(
|
||||
characterizationRules(
|
||||
;( rule layer1 layer2 value )
|
||||
;( ---- ------ ------ ----- )
|
||||
( areaCap "P2Con" 0.0 )
|
||||
( areaCap "Poly2" 0.0 )
|
||||
( areaCap "Active" 0.0 )
|
||||
( areaCap "Poly1" 6e-05 )
|
||||
( areaCap "P1Con" 0.0 )
|
||||
( areaCap "ActX" 0.0 )
|
||||
( areaCap "Metal1" 2.6e-05 )
|
||||
( areaCap "Via" 0.0 )
|
||||
( areaCap "Metal2" 1.6e-05 )
|
||||
( edgeCapacitance "P2Con" 0.0 )
|
||||
( edgeCapacitance "Poly2" 0.0 )
|
||||
( edgeCapacitance "Active" 0.0 )
|
||||
( edgeCapacitance "Poly1" 0.0 )
|
||||
( edgeCapacitance "P1Con" 0.0 )
|
||||
( edgeCapacitance "ActX" 0.0 )
|
||||
( edgeCapacitance "Metal1" 0.0 )
|
||||
( edgeCapacitance "Via" 0.0 )
|
||||
( edgeCapacitance "Metal2" 0.0 )
|
||||
( sheetRes "P2Con" 0.0 )
|
||||
( sheetRes "Poly2" 0.0 )
|
||||
( sheetRes "Active" 0.0 )
|
||||
( sheetRes "Poly1" 23.0 )
|
||||
( sheetRes "P1Con" 0.0 )
|
||||
( sheetRes "ActX" 0.0 )
|
||||
( sheetRes "Metal1" 0.04 )
|
||||
( sheetRes "Via" 0.0 )
|
||||
( sheetRes "Metal2" 0.07 )
|
||||
( currentDensity "P2Con" 1.0 )
|
||||
( currentDensity "Poly2" 1.0 )
|
||||
( currentDensity "Active" 1.0 )
|
||||
( currentDensity "Poly1" 1.0 )
|
||||
( currentDensity "P1Con" 1.0 )
|
||||
( currentDensity "ActX" 1.0 )
|
||||
( currentDensity "Metal1" 1.0 )
|
||||
( currentDensity "Via" 1.0 )
|
||||
( currentDensity "Metal2" 1.0 )
|
||||
) ;characterizationRules
|
||||
|
||||
) ;electricalRules
|
||||
|
||||
|
||||
;********************************
|
||||
; LAYOUT EDITOR RULES
|
||||
;********************************
|
||||
; specifies the ordering of the layers in the LSW
|
||||
|
||||
leRules(
|
||||
leLswLayers(
|
||||
;( layer purpose )
|
||||
; ----- ------- )
|
||||
( Nwell drawing )
|
||||
( Pselect drawing )
|
||||
( Nselect drawing )
|
||||
( Active drawing )
|
||||
( ActX drawing )
|
||||
( Poly1 drawing )
|
||||
( P1Con drawing )
|
||||
( Metal1 drawing )
|
||||
( Via drawing )
|
||||
( Metal2 drawing )
|
||||
( Via2 drawing )
|
||||
( Metal3 drawing )
|
||||
( Poly1 pin )
|
||||
( Metal1 pin )
|
||||
( Metal2 pin )
|
||||
( Metal3 pin )
|
||||
( Poly2 drawing )
|
||||
( P2Con drawing )
|
||||
( instance drawing )
|
||||
( text drawing )
|
||||
( CapWell drawing )
|
||||
( SiBlock drawing )
|
||||
( HR drawing )
|
||||
( Pbase drawing )
|
||||
( Resistor drawing )
|
||||
( Capacitor drawing )
|
||||
( Diode drawing )
|
||||
( Glass drawing )
|
||||
( XP drawing )
|
||||
|
||||
) ;leLswLayers
|
||||
) ;leRules
|
||||
|
||||
|
||||
;********************************
|
||||
; VIRTUOSO XL RULES
|
||||
;********************************
|
||||
; specifies the ordering of the layers in the LSW
|
||||
|
||||
lxRules(
|
||||
lxExtractLayers(
|
||||
(Metal1 Metal2 Metal3)
|
||||
) ;lxExtractLayers
|
||||
) ;lxRules
|
||||
|
||||
Loading…
Reference in New Issue