mirror of https://github.com/openXC7/prjxray.git
Add support to zero db to support simple groups.
Previously these kinds of zero groups would require encoding the final bits, rather than tags. This is extends the dbfixup to construct groups via groups of tags, rather than groups of bits. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman
parent
0548c105e4
commit
01a0be3162
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@ -1,3 +1,4 @@
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N := 1
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CLB_DBFIXUP=Y
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include ../clb.mk
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@ -0,0 +1,3 @@
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# NOCLKINV is inverse of CLKINV
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CLB.SLICE_X0.CLKINV ^ CLB.SLICE_X0.NOCLKINV
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CLB.SLICE_X1.CLKINV ^ CLB.SLICE_X1.NOCLKINV
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@ -94,8 +94,10 @@ with open("design.txt", "r") as f:
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# CLKINV turns out to be more complicated than origianlly thought
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if isff(cel_prim):
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segmk.add_site_tag(site, "CLKINV", cinv)
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segmk.add_site_tag(site, "NOCLKINV", 1 ^ cinv)
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else:
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segmk.add_site_tag(site, "CLKINV", 1 ^ cinv)
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segmk.add_site_tag(site, "NOCLKINV", cinv)
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# Synchronous vs asynchronous FF
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# Unlike most bits, shared between all CLB FFs
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@ -1,4 +1,5 @@
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N := 3
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SLICEL ?= N
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CLB_DBFIXUP=Y
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include ../clb.mk
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@ -0,0 +1,3 @@
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CLB.SLICE_X0.ALUT.DI1MUX.AI ^ CLB.SLICE_X0.ALUT.DI1MUX.BDI1_BMC31
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CLB.SLICE_X0.BLUT.DI1MUX.BI ^ CLB.SLICE_X0.BLUT.DI1MUX.DI_CMC31
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CLB.SLICE_X0.CLUT.DI1MUX.CI ^ CLB.SLICE_X0.CLUT.DI1MUX.DI_DMC31
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@ -25,8 +25,11 @@ for l in f:
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b31 = int(b31)
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a31 = int(a31)
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segmk.add_site_tag(loc, "ALUT.DI1MUX.AI", 1 ^ a31)
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segmk.add_site_tag(loc, "ALUT.DI1MUX.BDI1_BMC31", a31)
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segmk.add_site_tag(loc, "BLUT.DI1MUX.BI", 1 ^ b31)
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segmk.add_site_tag(loc, "BLUT.DI1MUX.DI_CMC31", b31)
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segmk.add_site_tag(loc, "CLUT.DI1MUX.CI", 1 ^ c31)
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segmk.add_site_tag(loc, "CLUT.DI1MUX.DI_DMC31", c31)
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segmk.compile()
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segmk.write()
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273
utils/dbfixup.py
273
utils/dbfixup.py
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@ -51,57 +51,153 @@ def bits_str(bits):
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return ' '.join(sorted(list(bits)))
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def zero_groups(tag, bits, zero_db, strict=True, verbose=False):
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"""
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See if a line occurs within a bit group
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If it does, add 0 bits
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class ZeroGroups(object):
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def __init__(self, zero_db):
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self.groups = []
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self.bit_to_group = {}
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self.tag_to_groups = {}
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self.zero_tag_to_group = {}
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self.parse_zero_db(zero_db)
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Ex: 01_02 04_05
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Means find a line that has either of these bits
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If either of them occurs, default bits in that set to zero
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def print_groups(self):
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print('Zero groups:')
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for bits in self.groups:
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print(bits_str(bits))
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Ex: 01_02 04_05|07_08 10_11
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If any bits from the first group occur,
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default bits in the second group to zero
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print('Zero tags:')
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for tag in self.zero_tag_to_group:
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print(tag, bits_str(self.zero_tag_to_group[tag]))
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Ex: 01_02 04_05,ALL_ZERO
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ALL_ZERO is an enum that is part of the group but is all 0
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It must have 0 candidates
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def parse_zero_db(self, zero_db):
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""" Convert zero db format into data structure
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strict: assert that the size of the given group is the size of the given mask
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"""
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for zdb in zero_db:
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allzero_tag = None
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if "," in zdb:
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zdb, allzero_tag = zdb.split(",")
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Zero db format examples:
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if "|" in zdb:
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a, b = zdb.split("|")
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a = a.split()
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b = b.split()
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else:
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a = zdb.split()
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b = a
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Ex: 01_02 04_05
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Means find a line that has either of these bits
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If either of them occurs, default bits in that set to zero
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bitmatch = False
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for bit in a:
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if bit in bits:
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bitmatch = True
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Ex: 01_02 04_05|07_08 10_11
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If any bits from the first group occur,
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default bits in the second group to zero
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if not (bitmatch or allzero_tag == tag):
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continue
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Ex: 01_02 04_05,ALL_ZERO
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ALL_ZERO is an enum that is part of the group but is all 0
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It must have 0 candidates
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bits_orig = set(bits)
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for bit in b:
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if bit not in bits:
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Ex: CLB.SLICE_X0.CLKINV ^ CLB.SLICE_X0.NOCLKINV
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CLB.SLICE_X0.NOCLKINV is all bits in CLB.SLICE_X0.CLKINV unset
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Ex: A | B ^ C
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C is all bits in (A)|(B) unset
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"""
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for zdb in zero_db:
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if "^" in zdb:
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self.groups.append(set())
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zero_group = self.groups[-1]
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other_tags, allzero_tag = zdb.split('^')
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allzero_tag = allzero_tag.strip()
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for tag in other_tags.split():
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self.tag_to_groups[tag.strip()] = [zero_group]
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self.zero_tag_to_group[allzero_tag] = zero_group
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continue
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allzero_tag = None
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if "," in zdb:
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zdb, allzero_tag = zdb.split(",")
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if "|" in zdb:
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a, b = zdb.split("|")
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a = a.split()
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b = b.split()
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self.groups.append(set(b))
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zero_group = self.groups[-1]
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else:
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a = zdb.split()
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self.groups.append(set(a))
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zero_group = self.groups[-1]
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if allzero_tag is not None:
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self.zero_tag_to_group[allzero_tag] = zero_group
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for bit in a:
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self.bit_to_group[bit] = zero_group
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def add_tag_bits(self, tag, bits):
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if tag in self.zero_tag_to_group:
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assert len(bits) == 0
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return
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group_ids = set()
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groups = []
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if tag in self.tag_to_groups:
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assert len(self.tag_to_groups[tag]) == 1
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self.tag_to_groups[tag][0] |= bits
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for bit in bits:
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if bit in self.bit_to_group:
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# Make sure each bit only belongs to one group
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assert id(self.bit_to_group[bit]) == id(
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self.tag_to_groups[tag])
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else:
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self.bit_to_group[bit] = self.tag_to_groups[tag]
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group_ids.add(id(self.tag_to_groups[tag]))
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groups = self.tag_to_groups[tag]
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for bit in bits:
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if bit in self.bit_to_group:
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if id(self.bit_to_group[bit]) not in group_ids:
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group_ids.add(id(self.bit_to_group[bit]))
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groups.append(self.bit_to_group[bit])
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self.tag_to_groups[tag] = groups
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def add_bits_from_zero_groups(self, tag, bits, strict=True, verbose=False):
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""" Add bits from a zero group, if needed
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Arguments
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---------
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tag : str
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Tag being to examine for zero group
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bits : set of str
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Set of bits set on this tag
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strict : bool
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Assert that the size of the given group is the size of the given
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mask.
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verbose : bool
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Print to stdout grouping being made
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"""
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tag_is_masked = tag in self.tag_to_groups
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tag_is_zero = tag in self.zero_tag_to_group
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# Should not have a tag that is both masked and a zero tag.
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assert not (tag_is_masked and tag_is_zero)
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if tag_is_masked:
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for b in self.tag_to_groups[tag]:
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bits_orig = set(bits)
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for bit in b:
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if bit not in bits:
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bits.add("!" + bit)
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verbose and print(
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"Grouped %s: %s => %s" %
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(tag, bits_str(bits_orig), bits_str(bits)))
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if tag_is_zero:
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for bit in self.zero_tag_to_group[tag]:
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bits.add("!" + bit)
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verbose and print(
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"Grouped %s: %s => %s" %
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(tag, bits_str(bits_orig), bits_str(bits)))
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if a == b and strict:
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assert len(bits) == len(
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a), "Mask size %u != DB entry size %u: %s" % (
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len(a), len(bits), bits_str(bits))
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def add_zero_bits(fn_in, zero_db, clb_int=False, strict=True, verbose=False):
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@ -111,11 +207,15 @@ def add_zero_bits(fn_in, zero_db, clb_int=False, strict=True, verbose=False):
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If an entry has any of the
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'''
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zero_groups = ZeroGroups(zero_db)
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lines = []
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new_lines = set()
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changes = 0
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llast = None
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drops = 0
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with open(fn_in, "r") as f:
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for line in f:
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# Hack: skip duplicate lines
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@ -124,53 +224,64 @@ def add_zero_bits(fn_in, zero_db, clb_int=False, strict=True, verbose=False):
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if line == llast:
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continue
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lines.append(line)
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tag, bits, mode, _ = util.parse_db_line(line)
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# an enum that needs masking
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# check below asserts that a mask was actually applied
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if mode and mode != "<0 candidates>" and not strict:
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if bits is not None and mode is None:
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zero_groups.add_tag_bits(tag, bits)
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if verbose:
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zero_groups.print_groups()
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for line in lines:
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tag, bits, mode, _ = util.parse_db_line(line)
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# an enum that needs masking
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# check below asserts that a mask was actually applied
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if mode and mode != "<0 candidates>" and not strict:
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verbose and print("WARNING: dropping unresolved line: %s" % line)
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drops += 1
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continue
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assert mode not in (
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"<const0>",
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"<const1>"), "Entries must be resolved. line: %s" % (line, )
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if mode == "always":
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new_line = line
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else:
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if mode:
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assert mode == "<0 candidates>", line
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bits = set()
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else:
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bits = set(bits)
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"""
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This appears to be a large range of one hot interconnect bits
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They are immediately before the first CLB real bits
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"""
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if clb_int:
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zero_range(tag, bits, 22, 25)
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zero_groups.add_bits_from_zero_groups(
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tag, bits, strict=strict, verbose=verbose)
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if strict:
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assert len(bits) > 0, 'Line {} found no bits.'.format(line)
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elif len(bits) == 0:
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verbose and print(
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"WARNING: dropping unresolved line: %s" % line)
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drops += 1
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continue
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assert mode not in (
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"<const0>",
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"<const1>"), "Entries must be resolved. line: %s" % (line, )
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new_line = " ".join([tag] + sorted(bits))
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if mode == "always":
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new_line = line
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else:
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if mode:
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assert mode == "<0 candidates>", line
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bits = set()
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else:
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bits = set(bits)
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"""
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This appears to be a large range of one hot interconnect bits
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They are immediately before the first CLB real bits
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"""
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if clb_int:
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zero_range(tag, bits, 22, 25)
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zero_groups(tag, bits, zero_db, strict=strict, verbose=verbose)
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if re.match(r'.*<.*>.*', new_line):
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print("Original line: %s" % line)
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assert 0, "Failed to remove line mode: %s" % (new_line)
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if strict:
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assert len(bits) > 0, 'Line {} found no bits.'.format(line)
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elif len(bits) == 0:
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verbose and print(
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"WARNING: dropping unresolved line: %s" % line)
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drops += 1
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continue
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new_line = " ".join([tag] + sorted(bits))
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if re.match(r'.*<.*>.*', new_line):
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print("Original line: %s" % line)
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assert 0, "Failed to remove line mode: %s" % (new_line)
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if new_line != line:
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changes += 1
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new_lines.add(new_line)
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llast = line
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if new_line != line:
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changes += 1
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new_lines.add(new_line)
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llast = line
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if drops:
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print("WARNING: %s dropped %s unresolved lines" % (fn_in, drops))
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