mirror of https://github.com/openXC7/prjxray.git
fuzzers: 007: run make format
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
This commit is contained in:
parent
73979fdf04
commit
c9d661d161
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@ -2,6 +2,7 @@
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import argparse
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def fix_line(line, site, filetype):
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line = line.split()
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newline = list()
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@ -16,13 +17,13 @@ def fix_line(line, site, filetype):
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all_entries = 0
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loc = 2
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for site in range(0, sites_count):
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bels_count = int(line[loc + 1])
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loc += 2
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for bel in range(0, bels_count):
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entries_count = int(line[loc + 1])
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loc += 2
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all_entries += entries_count
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for entry in range(0, entries_count):
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bels_count = int(line[loc + 1])
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loc += 2
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for bel in range(0, bels_count):
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entries_count = int(line[loc + 1])
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loc += 2
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all_entries += entries_count
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for entry in range(0, entries_count):
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if filetype == 'timings':
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for delay_word in range(0, 6):
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entries.append(line[loc])
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@ -44,13 +45,19 @@ def fix_line(line, site, filetype):
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newline.extend(entries)
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return " ".join(newline) + "\n"
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def main():
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parser = argparse.ArgumentParser()
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parser.add_argument('--txtin', type=str, help='Input text file')
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parser.add_argument('--txtout', type=str, help='Output text file')
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parser.add_argument('--site', type=str, help='Site to which the entries should be squashed')
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parser.add_argument('--slice', type=str, help='Slice for which the entries shall be fixed')
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parser.add_argument('--type', type=str, choices=['timings', 'pins', 'properties'])
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parser.add_argument(
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'--site',
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type=str,
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help='Site to which the entries should be squashed')
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parser.add_argument(
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'--slice', type=str, help='Slice for which the entries shall be fixed')
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parser.add_argument(
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'--type', type=str, choices=['timings', 'pins', 'properties'])
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args = parser.parse_args()
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lines = list()
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@ -65,5 +72,6 @@ def main():
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for line in lines:
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fp.write(line)
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if __name__ == "__main__":
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main()
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@ -281,7 +281,8 @@ def read_raw_timings(fin, properties, pins, site_pins, pin_alias_map):
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# if we couldn't find input, check if the clock is the
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# only input. This applies only to combinational paths
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if (sequential is None) and (bel_input is None) and (bel_clock is not None):
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if (sequential is None) and (bel_input is None) and (
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bel_clock is not None):
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if bel_clock_orig_pin in site_pins[slice][site_name.lower()] and \
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site_pins[slice][site_name.lower(
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)][bel_clock_orig_pin]['direction'] == 'IN':
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@ -334,7 +335,6 @@ def read_raw_timings(fin, properties, pins, site_pins, pin_alias_map):
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orig_pin.lower(),
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speed_model_clean)
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# if we still don't have input, give up
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if bel_input is None:
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delay_loc += 6
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