mirror of https://github.com/openXC7/prjxray.git
Fuzzers: 007: add bel timing fuzzer
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
This commit is contained in:
Karol Gugala
Tim 'mithro' Ansell
parent
3ccc2df586
commit
5d9da26f78
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build
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debug*.json
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all: build/sdf
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clean:
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rm -rf build
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build/bel_timings.txt:
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bash runme.sh
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build/bel_timings.json: build/bel_timings.txt
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python3 tim2json.py --timings=build/bel_timings.txt --json=build/bel_timings.json --properties=build/bel_properties.txt --belpins=build/bel_pins.txt --sitepins=build/tile_pins.txt
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build/sdf: build/bel_timings.json
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python3 ${XRAY_UTILS_DIR}/makesdf.py --json=${PWD}/build/bel_timings.json --sdf=${PWD}/build
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touch run.ok
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#!/bin/bash
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set -ex
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# Create build dir
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export SRC_DIR=$PWD
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export BUILD_DIR=build
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mkdir -p $BUILD_DIR
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cd $BUILD_DIR
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${XRAY_VIVADO} -mode batch -source $SRC_DIR/runme.tcl
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test -z "$(fgrep CRITICAL vivado.log)" && touch run.ok
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source "$::env(XRAY_DIR)/utils/utils.tcl"
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proc create_design {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog $::env(SRC_DIR)/top.v
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synth_design -top top -flatten_hierarchy none
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports do]
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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}
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proc place_and_route_design {} {
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place_design
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route_design
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write_checkpoint -force design.dcp
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}
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proc dump_tile_timings {tile timing_fp config_fp pins_fp tile_pins_fp} {
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set properties [list "DELAY" "FAST_MAX" "FAST_MIN" "SLOW_MAX" "SLOW_MIN"]
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set timing_line {}
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set config_line {}
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set pins_line {}
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set tile_pins_line {}
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lappend timing_line [get_property TYPE $tile]
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lappend config_line [get_property TYPE $tile]
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lappend pins_line [get_property TYPE $tile]
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lappend tile_pins_line [get_property TYPE $tile]
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set sites [get_sites -of_objects [get_tiles $tile]]
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lappend tile_pins_line [llength $sites]
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lappend timing_line [llength $sites]
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lappend config_line [llength $sites]
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lappend pins_line [llength $sites]
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foreach site $sites {
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set site_type [get_property SITE_TYPE $site]
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lappend tile_pins_line $site_type
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lappend pins_line $site_type
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lappend timing_line $site_type
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lappend config_line $site_type
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# dump site pins
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set site_pins [get_site_pins -of_objects [get_sites $site]]
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lappend tile_pins_line [llength $site_pins]
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foreach pin $site_pins {
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set direction [get_property DIRECTION $pin]
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regexp {\/(.*)$} $pin -> pin
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lappend tile_pins_line $pin $direction
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}
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# dump bel pins, speed_models and configs
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set bels [get_bels -of_objects $site]
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lappend pins_line [llength $bels]
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lappend timing_line [llength $bels]
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lappend config_line [llength $bels]
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foreach bel $bels {
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set speed_models [get_speed_models -of_objects $bel]
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set bel_type [get_property TYPE $bel]
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set bel_configs [list_property $bel CONFIG*]
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set bel_pins [get_bel_pins -of_objects [get_bels $bel]]
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lappend pins_line $bel_type
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lappend pins_line [llength $bel_pins]
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foreach pin $bel_pins {
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set direction [get_property DIRECTION $pin]
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set is_clock [get_property IS_CLOCK $pin]
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regexp {\/.*\/(.*)$} $pin -> pin
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lappend pins_line $pin $direction $is_clock
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}
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lappend config_line $bel_type
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lappend config_line [llength $bel_configs]
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foreach config $bel_configs {
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set config_vals [get_property $config $bel]
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lappend config_line $config
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lappend config_line [llength $config_vals]
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foreach val $config_vals {
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lappend config_line $val
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}
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}
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lappend timing_line "$bel_type"
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lappend timing_line [llength $speed_models]
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foreach speed_model $speed_models {
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lappend timing_line $speed_model
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foreach property $properties {
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set value [get_property $property $speed_model]
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lappend timing_line "$property:$value"
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}
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}
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}
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}
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puts $tile_pins_fp $tile_pins_line
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puts $pins_fp $pins_line
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puts $timing_fp $timing_line
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puts $config_fp $config_line
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}
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proc dump {} {
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set types [get_tile_types]
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set timing_fp [open "bel_timings.txt" w]
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set property_fp [open "bel_properties.txt" w]
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set pins_fp [open "bel_pins.txt" w]
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set tile_pins_fp [open "tile_pins.txt" w]
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foreach type $types {
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set tile [randsample_list 1 [get_tiles -filter "TYPE == $type"]]
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dump_tile_timings $tile $timing_fp $property_fp $pins_fp $tile_pins_fp
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}
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close $pins_fp
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close $timing_fp
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close $property_fp
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}
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proc run {} {
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create_design
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place_and_route_design
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dump
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write_bitstream -force design.bit
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}
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run
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#!/usr/bin/env python3
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import argparse
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import json
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def check_sequential(speed_model):
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# combinational path models do not contain
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# the following keywords
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timing_keywords = {
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'setup': 'setup',
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'remov': 'removal',
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'hold': 'hold',
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'recov': 'recovery',
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'removal': 'removal',
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'recovery': 'recovery'
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}
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tmp = speed_model.split('_')
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for keyword in timing_keywords:
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if keyword in tmp:
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# return found keyword and it's map in SDF
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return [keyword, timing_keywords[keyword]]
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return None
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# FF's can be configured to work as FF or latch
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def check_ff_latch(speed_model):
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tmp = speed_model.split('_')
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if 'ff' in tmp:
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return 'ff'
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elif 'lat' in tmp:
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return 'lat'
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else:
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return None
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# some bels have duplicate names e.g bufmrce_bufmrce
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# this function cleans them
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def clean_bname(bname):
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tmp = bname.split('_')
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if len(tmp) > 1 and tmp[0] == tmp[1]:
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return '_'.join(tmp[1:])
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return bname
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def pin_in_model(pin, model):
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if len(pin.split('_')) == 1:
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# pin name is one word, search it in the model
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return pin in model.split('_')
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else:
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# pin name is multi word, search for a string
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return pin in model
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def remove_pin_from_model(pin, model):
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if len(pin.split('_')) == 1:
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# pin name is one word, search it in the model
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tmp = model.split('_')
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tmp.remove(pin)
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return "_".join(tmp)
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else:
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# pin name is multi word, search for a string
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return "_".join(
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list(filter(None,
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speed_model.replace(pin, '').split('_'))))
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def read_raw_timings(fin, properties, pins, site_pins):
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timings = dict()
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with open(fin, "r") as f:
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for line in f:
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raw_data = line.split()
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slice = raw_data[0]
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#XXX: debug
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if slice.startswith('DSP'):
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continue
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sites_count = int(raw_data[1])
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loc = 2
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timings[slice] = dict()
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for site in range(0, sites_count):
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site_name = raw_data[loc]
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bels_count = int(raw_data[loc + 1])
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print(slice, site_name)
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# read all BELs data within
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loc += 2
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for bel in range(0, bels_count):
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tmp_data = raw_data[loc:]
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btype = (tmp_data[0]).lower()
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delay_count = int(tmp_data[1])
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# get all the delays
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delay_loc = 2
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for delay in range(0, delay_count):
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speed_model = tmp_data[delay_loc]
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delay_btype = clean_bname(btype)
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delay_btype_orig = delay_btype
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# all the bel names seem to start with "bel_d_"
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# let's get rid of it
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if speed_model.startswith('bel_d_'):
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speed_model = speed_model[6:]
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# keep original speed model string to use as unique dict entry
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speed_model_orig = speed_model
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# if more than one BEL type exists in the slice
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# location is added at the end of the name
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tmp = speed_model.split(':')
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speed_model = tmp[0]
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bel_location = site_name
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if len(tmp) > 2:
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bel_location += "/" + "/".join(tmp[2:])
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bel_location = bel_location.upper()
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sequential = check_sequential(speed_model)
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if sequential is not None:
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tmp = speed_model.split('_')
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tmp.remove(sequential[0])
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speed_model = '_'.join(tmp)
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bel_input = None
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bel_output = None
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bel_clock = None
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# strip btype from speed model so we can search for pins
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speed_model_clean = speed_model
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if speed_model.startswith(delay_btype):
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speed_model_clean = speed_model[len(delay_btype):]
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# locate pins
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for pin in pins[slice][site_name][delay_btype_orig]:
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if pin_in_model(pin.lower(), speed_model_clean):
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if pins[slice][site_name][delay_btype_orig][
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pin]['direction'] == 'IN':
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bel_input = pin
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if pins[slice][site_name][delay_btype_orig][
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pin]['direction'] == 'OUT':
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bel_output = pin
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if pins[slice][site_name][delay_btype_orig][
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pin]['is_clock']:
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bel_clock = pin
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speed_model_clean = remove_pin_from_model(
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pin.lower(), speed_model_clean)
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# Some speed models describe delays from/to site pins instead of BEL pins
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if bel_input is None:
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# search site inputs
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for pin in site_pins[slice][site_name.lower()]:
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if pin_in_model(pin.lower(),
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speed_model_clean):
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if site_pins[slice][site_name.lower(
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)][pin]['direction'] == 'IN':
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bel_input = pin
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speed_model_clean = remove_pin_from_model(
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pin.lower(), speed_model_clean)
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if bel_output is None:
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for pin in site_pins[slice][site_name.lower()]:
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if pin_in_model(pin.lower(),
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speed_model_clean):
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if site_pins[slice][site_name.lower(
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)][pin]['direction'] == 'OUT':
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bel_output = pin
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speed_model_clean = remove_pin_from_model(
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pin.lower(), speed_model_clean)
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if bel_clock is None:
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for pin in site_pins[slice][site_name.lower()]:
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if pin_in_model(pin.lower(),
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speed_model_clean):
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if site_pins[slice][site_name.lower(
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)][pin]['is_clock']:
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bel_clock = pin
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speed_model_clean = remove_pin_from_model(
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pin.lower(), speed_model_clean)
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# restore speed model name
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speed_model = delay_btype + speed_model_clean
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if sequential is not None:
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if bel_output is None and bel_clock is None:
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delay_loc += 6
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continue
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else:
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if bel_input is None or bel_output is None:
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delay_loc += 6
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continue
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delay_btype = speed_model
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extra_ports = None
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if bel_location not in timings[slice]:
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timings[slice][bel_location] = dict()
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if delay_btype not in timings[slice][bel_location]:
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timings[slice][bel_location][delay_btype] = dict()
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timings[slice][bel_location][delay_btype][
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speed_model_orig] = dict()
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timings[slice][bel_location][delay_btype][
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speed_model_orig]['type'] = btype.upper()
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timings[slice][bel_location][delay_btype][
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speed_model_orig]['input'] = bel_input.upper()
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if bel_output is not None:
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timings[slice][bel_location][delay_btype][
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speed_model_orig]['output'] = bel_output.upper(
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)
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if bel_clock is not None:
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timings[slice][bel_location][delay_btype][
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speed_model_orig]['clock'] = bel_clock.upper()
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timings[slice][bel_location][delay_btype][
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speed_model_orig]['location'] = bel_location.upper(
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)
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#XXX: debug
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timings[slice][bel_location][delay_btype][
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speed_model_orig]['model'] = speed_model_orig
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if sequential is not None:
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timings[slice][bel_location][delay_btype][
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speed_model_orig]['sequential'] = sequential[1]
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if extra_ports is not None:
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timings[slice][bel_location][delay_btype][
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speed_model_orig]['extra_ports'] = extra_ports
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# each timing entry reports 5 delays
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for d in range(0, 5):
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(t, v) = tmp_data[d + 1 + delay_loc].split(':')
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timings[slice][bel_location][delay_btype][
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speed_model_orig][t] = v
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# 5 delay values + name
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delay_loc += 6
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loc += delay_loc
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return timings
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def read_bel_properties(properties_file):
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properties = dict()
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with open(properties_file, 'r') as f:
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for line in f:
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raw_props = line.split()
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tile = raw_props[0]
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sites_count = int(raw_props[1])
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prop_loc = 2
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properties[tile] = dict()
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for site in range(0, sites_count):
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site_name = raw_props[prop_loc]
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bels_count = int(raw_props[prop_loc + 1])
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prop_loc += 2
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properties[tile][site_name] = dict()
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for bel in range(0, bels_count):
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bel_name = raw_props[prop_loc]
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bel_name = clean_bname(bel_name)
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bel_name = bel_name.lower()
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bel_properties_count = int(raw_props[prop_loc + 1])
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properties[tile][site_name][bel_name] = dict()
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prop_loc += 2
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for prop in range(0, bel_properties_count):
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prop_name = raw_props[prop_loc]
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# the name always starts with "CONFIG." and ends with ".VALUES"
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# let's get rid of that
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prop_name = prop_name[7:-7]
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prop_values_count = int(raw_props[prop_loc + 1])
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properties[tile][site_name][bel_name][
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prop_name] = raw_props[prop_loc + 2:prop_loc + 2 +
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prop_values_count]
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prop_loc += 2 + prop_values_count
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return properties
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def read_bel_pins(pins_file):
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pins = dict()
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with open(pins_file, 'r') as f:
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for line in f:
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raw_pins = line.split()
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tile = raw_pins[0]
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sites_count = int(raw_pins[1])
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pin_loc = 2
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pins[tile] = dict()
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for site in range(0, sites_count):
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site_name = raw_pins[pin_loc]
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bels_count = int(raw_pins[pin_loc + 1])
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pin_loc += 2
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pins[tile][site_name] = dict()
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for bel in range(0, bels_count):
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bel_name = raw_pins[pin_loc]
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bel_name = clean_bname(bel_name)
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bel_name = bel_name.lower()
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bel_pins_count = int(raw_pins[pin_loc + 1])
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pins[tile][site_name][bel_name] = dict()
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pin_loc += 2
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for pin in range(0, bel_pins_count):
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pin_name = raw_pins[pin_loc]
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pin_direction = raw_pins[pin_loc + 1]
|
||||
pin_is_clock = raw_pins[pin_loc + 2]
|
||||
pins[tile][site_name][bel_name][pin_name] = dict()
|
||||
pins[tile][site_name][bel_name][pin_name][
|
||||
'direction'] = pin_direction
|
||||
pins[tile][site_name][bel_name][pin_name][
|
||||
'is_clock'] = int(pin_is_clock) == 1
|
||||
pin_loc += 3
|
||||
return pins
|
||||
|
||||
|
||||
def read_site_pins(pins_file):
|
||||
|
||||
pins = dict()
|
||||
with open(pins_file, 'r') as f:
|
||||
for line in f:
|
||||
raw_pins = line.split()
|
||||
tile = raw_pins[0]
|
||||
site_count = int(raw_pins[1])
|
||||
pin_loc = 2
|
||||
pins[tile] = dict()
|
||||
for site in range(0, site_count):
|
||||
site_name = raw_pins[pin_loc]
|
||||
site_name = site_name.lower()
|
||||
site_pins_count = int(raw_pins[pin_loc + 1])
|
||||
pins[tile][site_name] = dict()
|
||||
pin_loc += 2
|
||||
for pin in range(0, site_pins_count):
|
||||
pin_name = raw_pins[pin_loc]
|
||||
pin_direction = raw_pins[pin_loc + 1]
|
||||
pins[tile][site_name][pin_name] = dict()
|
||||
pins[tile][site_name][pin_name][
|
||||
'direction'] = pin_direction
|
||||
# site clock pins are always named 'CLK'
|
||||
pins[tile][site_name][pin_name][
|
||||
'is_clock'] = pin_name.lower() == 'clk'
|
||||
pin_loc += 2
|
||||
return pins
|
||||
|
||||
|
||||
def main():
|
||||
parser = argparse.ArgumentParser()
|
||||
parser.add_argument('--timings', type=str, help='Raw timing input file')
|
||||
parser.add_argument('--json', type=str, help='json output file')
|
||||
parser.add_argument(
|
||||
'--properties', type=str, help='Bel properties input file')
|
||||
parser.add_argument('--belpins', type=str, help='Bel pins input file')
|
||||
parser.add_argument('--sitepins', type=str, help='Site pins input file')
|
||||
parser.add_argument(
|
||||
'--debug', type=bool, default=False, help='Enable debug json dumps')
|
||||
args = parser.parse_args()
|
||||
properties = read_bel_properties(args.properties)
|
||||
|
||||
if args.debug:
|
||||
with open('debug_prop.json', 'w') as fp:
|
||||
json.dump(properties, fp, indent=4, sort_keys=True)
|
||||
|
||||
pins = read_bel_pins(args.belpins)
|
||||
if args.debug:
|
||||
with open('debug_pins.json', 'w') as fp:
|
||||
json.dump(pins, fp, indent=4, sort_keys=True)
|
||||
|
||||
site_pins = read_site_pins(args.sitepins)
|
||||
if args.debug:
|
||||
with open('debug_site_pins.json', 'w') as fp:
|
||||
json.dump(site_pins, fp, indent=4, sort_keys=True)
|
||||
|
||||
timings = read_raw_timings(args.timings, properties, pins, site_pins)
|
||||
with open(args.json, 'w') as fp:
|
||||
json.dump(timings, fp, indent=4, sort_keys=True)
|
||||
|
||||
|
||||
if __name__ == '__main__':
|
||||
main()
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
module top(input di, output do);
|
||||
|
||||
assign do = di;
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in New Issue