Merge pull request #838 from antmicro/041_clk_hrow_pips_timeout

041-clk-hrow-pips: Fix timeout and bit collision problems
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litghost 2019-06-25 09:18:44 -07:00 committed by GitHub
commit 5845918552
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4 changed files with 22 additions and 9 deletions

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@ -4,7 +4,7 @@ PIPLIST_TCL=$(FUZDIR)/clk_hrow_pip_list.tcl
TODO_RE=".*"
MAKETODO_FLAGS=--sides "bot_r,top_r" --pip-type ${PIP_TYPE} --seg-type clk_hrow --re $(TODO_RE)
MAKETODO_FLAGS=--sides "bot_r,top_r" --pip-type ${PIP_TYPE} --seg-type clk_hrow --re $(TODO_RE) --balance-wire-re "^CLK_HROW_" --balance-wire-cnt "2"
N = 50
# These PIPs all appear to be either a 2 bit solutions.

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@ -2,9 +2,16 @@
import os
import os.path
import re
from prjxray.segmaker import Segmaker
def src_has_active_bit(src):
if re.match(r"^CLK_HROW_CK_INT_[01]_[01]", src) is not None:
return False
return True
def main():
segmk = Segmaker("design.bits")
@ -113,6 +120,9 @@ def main():
for tile_type, srcs in clk_list.items():
for tile, pips_srcs_dsts in tiledata.items():
for src in srcs:
#Don't solve fake features
if not src_has_active_bit(src):
continue
if 'GCLK' not in src:
active = src in active_clks[tile]
segmk.add_tile_tag(tile, '{}_ACTIVE'.format(src), active)

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@ -86,8 +86,7 @@ $(eval $(call fuzzer,030-iob,005-tilegrid))
$(eval $(call fuzzer,035-iob-ilogic,005-tilegrid))
$(eval $(call fuzzer,036-iob-ologic,005-tilegrid))
$(eval $(call fuzzer,040-clk-hrow-config,005-tilegrid))
#Disable the longest running fuzzer to speed up test iterations
#$(eval $(call fuzzer,041-clk-hrow-pips,005-tilegrid))
$(eval $(call fuzzer,041-clk-hrow-pips,005-tilegrid))
$(eval $(call fuzzer,042-clk-bufg-config,005-tilegrid))
$(eval $(call fuzzer,043-clk-rebuf-pips,005-tilegrid))
$(eval $(call fuzzer,044-clk-bufg-pips,005-tilegrid))

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@ -34,6 +34,7 @@ def load_pipfile(pipfile, verbose=False):
def balance_todo_list(
pipfile,
todos,
balance_wire_re,
balance_wire_direction,
@ -52,6 +53,7 @@ def balance_todo_list(
specified with the --balance-wire-direction switch) will have at least the number
of entries specified with the --balance-wire-cnt switch in the final todo list.
"""
orig_todos, tile_type = load_pipfile(pipfile, verbose=verbose)
if balance_wire_re is not None:
todo_wires = {}
verbose and print("Start balancing the TODO list")
@ -83,8 +85,10 @@ def balance_todo_list(
if len(todo_wires[wire]) == balance_wire_cnt:
break
for wire, other_wires in todo_wires.items():
assert len(other_wires) >= balance_wire_cnt, "Len is " + str(
len(other_wires))
if len(other_wires) < balance_wire_cnt:
verbose and print(
"Warning: failed to balance the todo list for wire {}, there are only {} PIPs which meet the requirement: {}"
.format(wire, len(other_wires), other_wires))
for other_wire in other_wires:
line = tile_type + "."
if balance_wire_direction in "src":
@ -112,7 +116,6 @@ def maketodo(
050-intpips doesn't care about contents, but most fuzzers use the tile type prefix
'''
orig_todos, tile_type = load_pipfile(pipfile, verbose=verbose)
todos, tile_type = load_pipfile(pipfile, verbose=verbose)
verbose and print('%s: %u entries' % (pipfile, len(todos)))
verbose and print("pipfile todo sample: %s" % list(todos)[0])
@ -141,7 +144,8 @@ def maketodo(
todos.remove(tag)
else:
verbose and print(
"WARNING: couldnt remove %s (line %s)" % (tag, line))
"WARNING: couldnt remove %s (line %s)" %
(tag, line.strip()))
else:
verbose and print("WARNING: dbfile doesnt exist: %s" % dbfile)
verbose and print('Post db %s: %u entries' % (dbfile, len(todos)))
@ -166,8 +170,8 @@ def maketodo(
verbose and print('Print %u entries w/ %u drops' % (lines, drops))
balance_todo_list(
filtered_todos, balance_wire_re, balance_wire_direction,
balance_wire_cnt)
pipfile, filtered_todos, balance_wire_re, balance_wire_direction,
balance_wire_cnt, verbose)
for todo in filtered_todos:
print(todo)