mirror of https://github.com/openXC7/prjxray.git
Merge pull request #838 from antmicro/041_clk_hrow_pips_timeout
041-clk-hrow-pips: Fix timeout and bit collision problems
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commit
5845918552
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@ -4,7 +4,7 @@ PIPLIST_TCL=$(FUZDIR)/clk_hrow_pip_list.tcl
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TODO_RE=".*"
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MAKETODO_FLAGS=--sides "bot_r,top_r" --pip-type ${PIP_TYPE} --seg-type clk_hrow --re $(TODO_RE)
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MAKETODO_FLAGS=--sides "bot_r,top_r" --pip-type ${PIP_TYPE} --seg-type clk_hrow --re $(TODO_RE) --balance-wire-re "^CLK_HROW_" --balance-wire-cnt "2"
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N = 50
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# These PIPs all appear to be either a 2 bit solutions.
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@ -2,9 +2,16 @@
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import os
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import os.path
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import re
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from prjxray.segmaker import Segmaker
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def src_has_active_bit(src):
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if re.match(r"^CLK_HROW_CK_INT_[01]_[01]", src) is not None:
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return False
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return True
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def main():
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segmk = Segmaker("design.bits")
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@ -113,6 +120,9 @@ def main():
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for tile_type, srcs in clk_list.items():
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for tile, pips_srcs_dsts in tiledata.items():
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for src in srcs:
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#Don't solve fake features
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if not src_has_active_bit(src):
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continue
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if 'GCLK' not in src:
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active = src in active_clks[tile]
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segmk.add_tile_tag(tile, '{}_ACTIVE'.format(src), active)
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@ -86,8 +86,7 @@ $(eval $(call fuzzer,030-iob,005-tilegrid))
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$(eval $(call fuzzer,035-iob-ilogic,005-tilegrid))
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$(eval $(call fuzzer,036-iob-ologic,005-tilegrid))
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$(eval $(call fuzzer,040-clk-hrow-config,005-tilegrid))
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#Disable the longest running fuzzer to speed up test iterations
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#$(eval $(call fuzzer,041-clk-hrow-pips,005-tilegrid))
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$(eval $(call fuzzer,041-clk-hrow-pips,005-tilegrid))
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$(eval $(call fuzzer,042-clk-bufg-config,005-tilegrid))
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$(eval $(call fuzzer,043-clk-rebuf-pips,005-tilegrid))
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$(eval $(call fuzzer,044-clk-bufg-pips,005-tilegrid))
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@ -34,6 +34,7 @@ def load_pipfile(pipfile, verbose=False):
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def balance_todo_list(
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pipfile,
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todos,
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balance_wire_re,
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balance_wire_direction,
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@ -52,6 +53,7 @@ def balance_todo_list(
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specified with the --balance-wire-direction switch) will have at least the number
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of entries specified with the --balance-wire-cnt switch in the final todo list.
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"""
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orig_todos, tile_type = load_pipfile(pipfile, verbose=verbose)
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if balance_wire_re is not None:
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todo_wires = {}
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verbose and print("Start balancing the TODO list")
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@ -83,8 +85,10 @@ def balance_todo_list(
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if len(todo_wires[wire]) == balance_wire_cnt:
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break
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for wire, other_wires in todo_wires.items():
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assert len(other_wires) >= balance_wire_cnt, "Len is " + str(
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len(other_wires))
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if len(other_wires) < balance_wire_cnt:
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verbose and print(
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"Warning: failed to balance the todo list for wire {}, there are only {} PIPs which meet the requirement: {}"
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.format(wire, len(other_wires), other_wires))
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for other_wire in other_wires:
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line = tile_type + "."
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if balance_wire_direction in "src":
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@ -112,7 +116,6 @@ def maketodo(
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050-intpips doesn't care about contents, but most fuzzers use the tile type prefix
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'''
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orig_todos, tile_type = load_pipfile(pipfile, verbose=verbose)
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todos, tile_type = load_pipfile(pipfile, verbose=verbose)
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verbose and print('%s: %u entries' % (pipfile, len(todos)))
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verbose and print("pipfile todo sample: %s" % list(todos)[0])
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@ -141,7 +144,8 @@ def maketodo(
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todos.remove(tag)
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else:
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verbose and print(
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"WARNING: couldnt remove %s (line %s)" % (tag, line))
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"WARNING: couldnt remove %s (line %s)" %
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(tag, line.strip()))
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else:
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verbose and print("WARNING: dbfile doesnt exist: %s" % dbfile)
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verbose and print('Post db %s: %u entries' % (dbfile, len(todos)))
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@ -166,8 +170,8 @@ def maketodo(
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verbose and print('Print %u entries w/ %u drops' % (lines, drops))
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balance_todo_list(
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filtered_todos, balance_wire_re, balance_wire_direction,
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balance_wire_cnt)
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pipfile, filtered_todos, balance_wire_re, balance_wire_direction,
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balance_wire_cnt, verbose)
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for todo in filtered_todos:
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print(todo)
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