Fischer Moseley
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b87f8cbc48
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meta: move to lib.io and lib.mem, enable bidirectional mem tests on xilinx
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2024-07-17 18:51:05 -07:00 |
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Fischer Moseley
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753a3f9427
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meta: finish moving simulations to new async API
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2024-07-17 18:51:05 -07:00 |
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Fischer Moseley
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8fd943257c
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sim: update testbenches to async API
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2024-07-17 18:51:05 -07:00 |
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Fischer Moseley
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13bc196a34
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rename Nexys A7 to Nexys 4 DDR
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2024-05-12 10:35:18 -07:00 |
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Fischer Moseley
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bd452d94a4
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put test outputs in build/
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2024-03-06 16:40:54 -08:00 |
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Fischer Moseley
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71ec1174d1
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add parameterized HW tests for all memory core modes
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2024-03-06 14:53:27 -08:00 |
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Fischer Moseley
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d1a772784a
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add environment.sh for tool paths and serial ports
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2024-03-06 11:26:31 -08:00 |
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Fischer Moseley
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5d5a50042f
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make model tracking automatic in memory core tests
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2024-03-06 01:12:36 -08:00 |
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Fischer Moseley
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c1935bcb11
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add random memory core tests
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2024-03-05 23:59:42 -08:00 |
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Fischer Moseley
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fd22c9a9f4
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finish memory core test class
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2024-03-05 22:44:36 -08:00 |
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Fischer Moseley
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b00e4d0e60
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revert wiring.Component instead of Elaboratable
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2024-03-04 01:18:31 -08:00 |
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Fischer Moseley
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5531277c99
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even more MemoryCore tests
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2024-03-04 00:43:54 -08:00 |
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Fischer Moseley
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f83dc59b4e
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add more MemoryCore tests
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2024-03-04 00:17:36 -08:00 |
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Fischer Moseley
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08adbd8ede
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switch to wiring.Component instead of Elaboratable
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2024-03-03 19:10:06 -08:00 |
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Fischer Moseley
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be79ba28b5
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define ABC for cores to inherit from
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2024-03-03 18:53:08 -08:00 |
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Fischer Moseley
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b729deb144
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hardcode device paths in hardware tests
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2024-03-03 18:31:11 -08:00 |
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Fischer Moseley
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11022f474d
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refactor Memory Core simulation into test class
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2024-03-03 13:30:54 -08:00 |
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Fischer Moseley
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e2d52a6e2d
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add simulate decorator
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2024-03-03 02:14:12 -08:00 |
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Fischer Moseley
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2e2397013e
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make mem_core_hw tests pass
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2024-03-02 14:08:52 -08:00 |
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Fischer Moseley
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6438a55192
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partially revert MemoryCore updates
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2024-03-02 13:31:01 -08:00 |
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Fischer Moseley
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6aea5cc6e1
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update MemoryCore references
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2024-03-02 12:52:04 -08:00 |
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Fischer Moseley
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ab7d9105b1
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add preliminary bidirectional memory core
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2024-02-28 10:36:27 -08:00 |
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Fischer Moseley
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b0dcd269bc
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add from_config to memory_core
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2024-02-19 11:42:28 -08:00 |
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Fischer Moseley
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7ee51158d2
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enforce consistent docstrings and underscores in logic analyzer core
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2024-02-19 11:23:11 -08:00 |
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Fischer Moseley
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e2450ddbff
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complete IO core refactor
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2024-02-18 15:50:51 -08:00 |
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Fischer Moseley
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0c0f31be64
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rewrite IO Core
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2024-02-18 13:50:26 -08:00 |
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Fischer Moseley
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a75a6a3ccf
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add first pass at ethernet
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2024-01-28 21:54:46 -08:00 |
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Fischer Moseley
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ee4a79a4d4
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refactor logic analyzer FSM to be sequential-only for better timing
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2024-01-21 23:45:14 -08:00 |
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Fischer Moseley
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ab0909d06b
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refactor logic analyzer to use enums, add incremental + immediate trigger modes
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2024-01-20 21:59:42 -08:00 |
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Fischer Moseley
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6e3fe8cb0e
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add initial FSM tests
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2024-01-20 15:25:04 -08:00 |
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Fischer Moseley
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a8b43849ec
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remove trig_blk test - was not adding value
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2024-01-15 12:33:59 -08:00 |
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Fischer Moseley
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edd00310c4
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first pass at logic analyzer trigger block tests
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2024-01-14 14:49:02 -08:00 |
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Fischer Moseley
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1528f569ef
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update submodule usage, tidy logic analyzer config check
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2024-01-14 12:51:52 -08:00 |
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Fischer Moseley
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487b11f155
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complete refactor to InternalBus()
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2024-01-07 22:35:15 -08:00 |
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Fischer Moseley
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a7625ce0a4
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refactor uart into multiple files
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2024-01-07 21:54:14 -08:00 |
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Fischer Moseley
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7a6ab45b92
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revert UART and InternalBus() refactor
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2024-01-07 21:39:44 -08:00 |
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Fischer Moseley
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ee4a3026af
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refactor to use common bus layout across all modules
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2024-01-07 18:17:09 -08:00 |
fischerm
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61d6479805
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add docstrings
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2024-01-07 15:13:35 -08:00 |
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Fischer Moseley
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4c48035201
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track amaranth release, not main repo
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2024-01-07 12:49:20 -08:00 |
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Fischer Moseley
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958ccadbd0
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refactored logic analyzer working in sim
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2024-01-05 21:43:53 -08:00 |
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Fischer Moseley
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a11605b2b7
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refactor logic analyzer
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2024-01-05 16:50:25 -08:00 |
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Fischer Moseley
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ee18e10ae1
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add immediate capture mode to logic analyzer
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2024-01-03 13:35:09 -07:00 |
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Fischer Moseley
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bc616fd3bf
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inital source, imported from splat
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2023-12-28 14:22:29 -08:00 |
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Fischer Moseley
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060583d8fc
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add working io_core autogeneration
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2023-09-04 23:03:49 -04:00 |
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Fischer Moseley
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49021411ea
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add beginnings of working io_core with CDC/large inputs
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2023-09-04 23:03:49 -04:00 |
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Fischer Moseley
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23418066f9
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remove uart_rx formal
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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f902d07b1d
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update read responses to use D as preamble
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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4abc2e2cae
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update template naming for consistency
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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7ed4a9e6b8
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polish uart testbenches
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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56b2442df7
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move uart code for verification to test/
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2023-09-02 11:39:16 -04:00 |