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add environment.sh for tool paths and serial ports

This commit is contained in:
Fischer Moseley 2024-03-06 11:26:31 -08:00
parent 5d5a50042f
commit d1a772784a
4 changed files with 21 additions and 7 deletions
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11
environment.sh Normal file
View File

@ -0,0 +1,11 @@
#!/usr/bin/env bash
export VIVADO=/tools/Xilinx/Vivado/2023.1/bin/vivado
export YOSYS=/tools/oss-cad-suite/bin/yosys
export NEXTPNR_ICE40=/tools/oss-cad-suite/bin/nextpnr-ice40
export ICEPACK=/tools/oss-cad-suite/bin/icepack
export ICEPROG=/tools/oss-cad-suite/bin/iceprog
export NEXYS4DDR_PORT=/dev/serial/by-id/usb-Digilent_Digilent_USB_Device_210292696307-if01-port0
export ICESTICK_PORT=/dev/serial/by-id/usb-Lattice_Lattice_FTUSB_Interface_Cable-if01-port0

5
test/test_io_core_hw.py
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@ -5,6 +5,7 @@ from manta import Manta
from manta.utils import *
import pytest
from random import getrandbits
import os
class IOCoreLoopbackTest(Elaboratable):
@ -143,11 +144,11 @@ class IOCoreLoopbackTest(Elaboratable):
@pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed")
def test_output_probe_initial_values_xilinx():
port = "/dev/serial/by-id/usb-Digilent_Digilent_USB_Device_210292696307-if01-port0"
port = os.environ["NEXYS4DDR_PORT"]
IOCoreLoopbackTest(Nexys4DDRPlatform(), port).verify()
@pytest.mark.skipif(not ice40_tools_installed(), reason="no toolchain installed")
def test_output_probe_initial_values_ice40():
port = "/dev/serial/by-id/usb-Lattice_Lattice_FTUSB_Interface_Cable-if01-port0"
port = os.environ["ICESTICK_PORT"]
IOCoreLoopbackTest(ICEStickPlatform(), port).verify()

5
test/test_logic_analyzer_hw.py
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@ -4,6 +4,7 @@ from amaranth_boards.icestick import ICEStickPlatform
from manta import Manta
from manta.utils import *
import pytest
import os
class LogicAnalyzerCounterTest(Elaboratable):
@ -78,11 +79,11 @@ class LogicAnalyzerCounterTest(Elaboratable):
@pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed")
def test_logic_analyzer_core_xilinx():
port = "/dev/serial/by-id/usb-Digilent_Digilent_USB_Device_210292696307-if01-port0"
port = os.environ["NEXYS4DDR_PORT"]
LogicAnalyzerCounterTest(Nexys4DDRPlatform(), port).verify()
@pytest.mark.skipif(not ice40_tools_installed(), reason="no toolchain installed")
def test_logic_analyzer_core_ice40():
port = "/dev/serial/by-id/usb-Lattice_Lattice_FTUSB_Interface_Cable-if01-port0"
port = os.environ["ICESTICK_PORT"]
LogicAnalyzerCounterTest(ICEStickPlatform(), port).verify()

7
test/test_mem_core_hw.py
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@ -4,8 +4,9 @@ from amaranth_boards.icestick import ICEStickPlatform
from manta import Manta
from manta.utils import *
import pytest
from random import randint, getrandbits
from random import getrandbits
from math import ceil, log2
import os
"""
Fundamentally we want a function to generate a configuration (as a dictionary)
@ -112,13 +113,13 @@ class MemoryCoreLoopbackTest(Elaboratable):
@pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed")
def test_mem_core_xilinx():
port = "/dev/serial/by-id/usb-Digilent_Digilent_USB_Device_210292696307-if01-port0"
port = os.environ["NEXYS4DDR_PORT"]
MemoryCoreLoopbackTest(Nexys4DDRPlatform(), 33, 1024, port).verify()
@pytest.mark.skipif(not ice40_tools_installed(), reason="no toolchain installed")
def test_mem_core_ice40():
port = "/dev/serial/by-id/usb-Lattice_Lattice_FTUSB_Interface_Cable-if01-port0"
port = os.environ["ICESTICK_PORT"]
MemoryCoreLoopbackTest(ICEStickPlatform(), 1, 2, port).verify()
MemoryCoreLoopbackTest(ICEStickPlatform(), 1, 512, port).verify()
MemoryCoreLoopbackTest(ICEStickPlatform(), 1, 1024, port).verify()