put test outputs in build/

src/manta/utils.py

@@ -2,7 +2,8 @@ from amaranth import *
 from amaranth.lib import data
 from amaranth.sim import Simulator
 from abc import ABC, abstractmethod
-from random import sample, randint
+from random import sample
+from pathlib import Path
 import os
 
 
@@ -114,22 +115,30 @@ def split_into_chunks(data, chunk_size):
 
     return [data[i : i + chunk_size] for i in range(0, len(data), chunk_size)]
 
+def make_build_dir_if_it_does_not_exist_already():
+    """
+    Make build/ if it doesn't exist already.
+    """
+
+    Path("build").mkdir(parents=True, exist_ok=True)
+
 
 def simulate(top):
     """
     A decorator for running behavioral simulation using Amaranth's built-in
     simulator. Requires the top-level module in the simulation as an argument,
-    and automatically names VCD file containing the waveform dump with the name
-    of the function being decorated.
+    and automatically names VCD file containing the waveform dump in build/
+    with the name of the function being decorated.
     """
 
     def decorator(testbench):
+        make_build_dir_if_it_does_not_exist_already()
         def wrapper(*args, **kwargs):
             sim = Simulator(top)
             sim.add_clock(1e-6)  # 1 MHz
             sim.add_sync_process(testbench)
 
-            vcd_path = testbench.__name__ + ".vcd"
+            vcd_path = "build/" + testbench.__name__ + ".vcd"
 
             with sim.write_vcd(vcd_path):
                 sim.run()

test/test_logic_analyzer_hw.py

@@ -59,14 +59,16 @@ class LogicAnalyzerCounterTest(Elaboratable):
         self.build_and_program()
         cap = self.manta.la.capture()
 
+        make_build_dir_if_it_does_not_exist_already()
+
         # check that VCD export works
-        cap.export_vcd("out.vcd")
+        cap.export_vcd("build/logic_analyzer_capture.vcd")
 
         # check that CSV export works
-        cap.export_csv("out.csv")
+        cap.export_csv("build/logic_analyzer_capture.csv")
 
         # check that Verilog export works
-        cap.export_playback_verilog("out.v")
+        cap.export_playback_verilog("build/logic_analzyer_capture_playback.v")
 
         # verify that each signal is just a counter modulo the width of the signal
         for name, width in self.manta.la._config["probes"].items():