add preliminary bidirectional memory core
This commit is contained in:
Fischer Moseley
parent
8a2b9ced76
commit
ab7d9105b1
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@ -1,6 +1,6 @@
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from amaranth import *
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from manta.utils import *
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from manta.memory_core import ReadOnlyMemoryCore
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from manta.memory_core import MemoryCore
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from manta.logic_analyzer.trigger_block import LogicAnalyzerTriggerBlock
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from manta.logic_analyzer.fsm import LogicAnalyzerFSM, States, TriggerModes
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from manta.logic_analyzer.playback import LogicAnalyzerPlayback
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@ -3,7 +3,7 @@ from manta.uart import UARTInterface
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from manta.ethernet import EthernetInterface
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from manta.io_core import IOCore
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from manta.memory_core import ReadOnlyMemoryCore
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from manta.memory_core import MemoryCore
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from manta.logic_analyzer import LogicAnalyzerCore
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@ -1,12 +1,13 @@
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from amaranth import *
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from amaranth.lib.memory import Memory
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from manta.utils import *
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from math import ceil
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class ReadOnlyMemoryCore(Elaboratable):
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class MemoryCore(Elaboratable):
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"""
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A module for generating a memory on the FPGA, with a read port tied to
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Manta's internal bus, and a write port provided to user logic.
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A module for generating a memory on the FPGA, with a port tied to Manta's
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internal bus, and a port provided to user logic.
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Provides methods for generating synthesizable logic for the FPGA, as well
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as methods for reading and writing the value of a register.
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@ -15,24 +16,50 @@ class ReadOnlyMemoryCore(Elaboratable):
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https://fischermoseley.github.io/manta/memory_core/
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"""
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def __init__(self, width, depth, base_addr, interface):
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def __init__(self, mode, width, depth, base_addr, interface):
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self._mode = mode
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self._width = width
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self._depth = depth
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self._base_addr = base_addr
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self._interface = interface
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self._max_addr = self._base_addr + (self._depth * ceil(self._width / 16))
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self._n_brams = ceil(self._width / 16)
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self._max_addr = self._base_addr + (self._depth * self._n_brams)
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# Bus Connections
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self.bus_i = Signal(InternalBus())
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self.bus_o = Signal(InternalBus())
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# User Port
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self.user_addr = Signal(range(self._depth))
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self.user_data = Signal(self._width)
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self.user_we = Signal(1)
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# User Ports
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if self._mode == "fpga_to_host":
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self.user_addr = Signal(range(self._depth))
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self.user_data_in = Signal(self._width)
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self.user_write_enable = Signal()
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self._top_level_ports = [
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self.user_addr,
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self.user_data_in,
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self.user_write_enable,
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]
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self._define_mems()
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elif self._mode == "host_to_fpga":
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self.user_addr = Signal(range(self._depth))
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self.user_data_out = Signal(self._width)
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self._top_level_ports = [
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self.user_addr,
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self.user_data_out,
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]
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elif self._mode == "bidirectional":
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self.user_addr = Signal(range(self._depth))
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self.user_data_in = Signal(self._width)
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self.user_data_out = Signal(self._width)
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self.user_write_enable = Signal()
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self._top_level_ports = [
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self.user_addr,
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self.user_data_in,
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self.user_data_out,
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self.user_write_enable,
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]
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@classmethod
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def from_config(cls, config, base_addr, interface):
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@ -64,9 +91,86 @@ class ReadOnlyMemoryCore(Elaboratable):
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if not width > 0:
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raise ValueError("Width of memory core must be positive. ")
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return cls(width, depth, base_addr, interface)
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# Check mode is provided and is recognized value
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mode = config.get("mode")
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if not mode:
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raise ValueError("Mode of memory core must be specified.")
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def _pipeline_bus(self, m):
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if mode not in ["fpga_to_host", "host_to_fpga", "bidirectional"]:
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raise ValueError("Unrecognized mode provided to memory core.")
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return cls(mode, width, depth, base_addr, interface)
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def _tie_mems_to_bus(self, m):
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for i, mem in enumerate(self._mems):
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# Compute address range corresponding to this chunk of memory
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start_addr = self._base_addr + (i * self._depth)
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stop_addr = start_addr + self._depth - 1
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# Handle write ports
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if self._mode in ["host_to_fpga", "bidirectional"]:
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write_port = mem.write_port()
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m.d.sync += write_port.data.eq(self.bus_i.data)
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m.d.sync += write_port.en.eq(self.bus_i.rw)
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m.d.sync += write_port.addr.eq(self.bus_i.addr - start_addr)
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# Handle read ports
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if self._mode in ["fpga_to_host", "bidirectional"]:
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read_port = mem.read_port()
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m.d.comb += read_port.en.eq(1)
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# Throw BRAM operations into the front of the pipeline
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with m.If(
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(self.bus_i.valid)
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& (self.bus_i.addr >= start_addr)
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& (self.bus_i.addr <= stop_addr)
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):
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m.d.sync += read_port.addr.eq(self.bus_i.addr - start_addr)
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# Pull BRAM reads from the back of the pipeline
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with m.If(
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(self._bus_pipe[2].valid)
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& (self._bus_pipe[2].addr >= start_addr)
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& (self._bus_pipe[2].addr <= stop_addr)
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):
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m.d.sync += self.bus_o.data.eq(read_port.data)
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def _tie_mems_to_user_logic(self, m):
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# Handle write ports
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if self._mode in ["fpga_to_host", "bidirectional"]:
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for i, mem in enumerate(self._mems):
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write_port = mem.write_port()
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m.d.comb += write_port.addr.eq(self.user_addr)
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m.d.comb += write_port.data.eq(self.user_data_in[16 * i : 16 * (i + 1)])
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m.d.comb += write_port.en.eq(self.user_write_enable)
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# Handle read ports
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if self._mode in ["host_to_fpga", "bidirectional"]:
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read_datas = []
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for i, mem in enumerate(self._mems):
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read_port = mem.read_port()
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m.d.comb += read_port.addr.eq(self.user_addr)
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m.d.comb += read_port.en.eq(1)
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read_datas.append(read_port.data)
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m.d.comb += self.user_data_out.eq(Cat(read_datas))
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def elaborate(self, platform):
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m = Module()
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# Define memories
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n_full = self._width // 16
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n_partial = self._width % 16
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self._mems = [Memory(shape=16, depth=self._depth, init=[0]*self._depth) for _ in range(n_full)]
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if n_partial > 0:
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self._mems += [Memory(shape=n_partial, depth=self._depth, init=[0]*self._depth)]
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# Add memories as submodules
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for i, mem in enumerate(self._mems):
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m.submodules[f"mem_{i}"] = mem
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# Pipeline the bus to accomodate the two clock-cycle delay in the memories
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self._bus_pipe = [Signal(InternalBus()) for _ in range(3)]
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m.d.sync += self._bus_pipe[0].eq(self.bus_i)
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@ -75,75 +179,9 @@ class ReadOnlyMemoryCore(Elaboratable):
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m.d.sync += self.bus_o.eq(self._bus_pipe[2])
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def _define_mems(self):
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# There's three cases that must be handled:
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# 1. Integer number of 16 bit mems
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# 2. Integer number of 16 bit mems + partial mem
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# 3. Just the partial mem (width < 16)
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# Only one, partial-width memory is needed
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if self._width < 16:
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self._mems = [Memory(depth=self._depth, width=self._width)]
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# Only full-width memories are needed
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elif self._width % 16 == 0:
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self._mems = [
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Memory(depth=self._depth, width=16) for _ in range(self._width // 16)
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]
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# Both full-width and partial memories are needed
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else:
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self._mems = [
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Memory(depth=self._depth, width=16) for i in range(self._width // 16)
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]
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self._mems += [Memory(depth=self._depth, width=self._width % 16)]
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def _handle_read_ports(self, m):
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# These are tied to the bus
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for i, mem in enumerate(self._mems):
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read_port = mem.read_port()
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m.d.comb += read_port.en.eq(1)
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start_addr = self._base_addr + (i * self._depth)
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stop_addr = start_addr + self._depth - 1
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# Throw BRAM operations into the front of the pipeline
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with m.If(
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(self.bus_i.valid)
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& (~self.bus_i.rw)
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& (self.bus_i.addr >= start_addr)
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& (self.bus_i.addr <= stop_addr)
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):
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m.d.sync += read_port.addr.eq(self.bus_i.addr - start_addr)
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# Pull BRAM reads from the back of the pipeline
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with m.If(
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(self._bus_pipe[2].valid)
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& (~self._bus_pipe[2].rw)
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& (self._bus_pipe[2].addr >= start_addr)
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& (self._bus_pipe[2].addr <= stop_addr)
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):
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m.d.sync += self.bus_o.data.eq(read_port.data)
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def _handle_write_ports(self, m):
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# These are given to the user
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for i, mem in enumerate(self._mems):
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write_port = mem.write_port()
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m.d.comb += write_port.addr.eq(self.user_addr)
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m.d.comb += write_port.data.eq(self.user_data[16 * i : 16 * (i + 1)])
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m.d.comb += write_port.en.eq(self.user_we)
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def elaborate(self, platform):
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m = Module()
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# Add memories as submodules
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for i, mem in enumerate(self._mems):
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m.submodules[f"mem_{i}"] = mem
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self._pipeline_bus(m)
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self._handle_read_ports(m)
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self._handle_write_ports(m)
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# Tie memory ports to the internal bus and user logic
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self._tie_mems_to_bus(m)
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self._tie_mems_to_user_logic(m)
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return m
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def get_top_level_ports(self):
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@ -151,7 +189,7 @@ class ReadOnlyMemoryCore(Elaboratable):
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Return the Amaranth signals that should be included as ports in the
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top-level Manta module.
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"""
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return [self.user_addr, self.user_data, self.user_we]
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return self._top_level_ports
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def get_max_addr(self):
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"""
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@ -161,26 +199,64 @@ class ReadOnlyMemoryCore(Elaboratable):
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"""
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return self._max_addr
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def read_from_user_addr(self, addrs):
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def _convert_user_to_bus_addr(self, addrs):
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"""
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Convert user address space to bus address space. For instance, for a
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core with base address 10 and width 33, reading from address 4 is
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actually a read from address 14 and address 14 + depth, and address
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14 + (2 * depth).
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"""
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if isinstance(addrs, int):
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return self._convert_user_to_bus_addr([addrs])[0]
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bus_addrs = []
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for addr in addrs:
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for i in range(len(self._mems)):
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bus_addrs.append(self._base_addr + addr + (i * self._depth))
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return bus_addrs
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def read(self, addrs):
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"""
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Read the memory stored at the provided address, as seen from the user
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side.
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"""
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# Convert user address space to bus address space
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# (for instance, for a core with base address 10 and width 33,
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# reading from address 4 is actually a read from address 14
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# and address 14 + depth, and address 14 + 2*depth)
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# Handle a single integer address
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if isinstance(addrs, int):
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return self.read_from_user_addr([addrs])[0]
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return self.read([addrs])[0]
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bus_addrs = []
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for addr in addrs:
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bus_addrs += [
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addr + self._base_addr + i * self._depth for i in range(len(self._mems))
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]
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# Make sure all list elements are integers
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if not all(isinstance(a, int) for a in addrs):
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raise TypeError("Read address must be an integer or list of integers.")
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bus_addrs = self._convert_user_to_bus_addr(addrs)
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datas = self._interface.read(bus_addrs)
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data_chunks = split_into_chunks(datas, len(self._mems))
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data_chunks = split_into_chunks(datas, self._n_brams)
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return [words_to_value(chunk) for chunk in data_chunks]
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def write(self, addrs, datas):
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"""
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Write to the memory stored at the provided address, as seen from the
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user side.
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"""
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# Handle a single integer address and data
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if isinstance(addrs, int) and isinstance(datas, int):
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return self.write([addrs], [datas])
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# Make sure address and datas are all integers
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if not isinstance(addrs, list) or not isinstance(datas, list):
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raise TypeError(
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"Write addresses and data must be an integer or list of integers."
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)
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if not all(isinstance(a, int) for a in addrs):
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raise TypeError("Write addresses must be all be integers.")
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if not all(isinstance(d, int) for d in datas):
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raise TypeError("Write data must all be integers.")
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bus_addrs = self._convert_user_to_bus_addr([addrs])[0]
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bus_datas = [word for d in datas for word in value_to_words(d, self._n_brams)]
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self._interface.write(bus_addrs, bus_datas)
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@ -1,4 +1,4 @@
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from manta.memory_core import ReadOnlyMemoryCore
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from manta.memory_core import MemoryCore
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from manta.utils import *
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from random import randint, sample
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@ -6,16 +6,16 @@ from random import randint, sample
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def fill_mem_from_user_port(mem_core, depth):
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for i in range(depth):
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yield mem_core.user_addr.eq(i)
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yield mem_core.user_data.eq(i)
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yield mem_core.user_we.eq(1)
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yield mem_core.user_data_in.eq(i)
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yield mem_core.user_write_enable.eq(1)
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yield
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yield mem_core.user_we.eq(0)
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yield mem_core.user_write_enable.eq(0)
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yield
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def verify_mem_core(width, depth, base_addr):
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mem_core = ReadOnlyMemoryCore(width, depth, base_addr, interface=None)
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mem_core = MemoryCore("fpga_to_host", width, depth, base_addr, interface=None)
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def testbench():
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yield from fill_mem_from_user_port(mem_core, depth)
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