move uart code for verification to test/

2023-07-19 19:18:43 -07:00 · 2023-07-19 19:18:43 -07:00 · 56b2442df7
parent d580419a5b
commit 56b2442df7
6 changed files with 1 additions and 8 deletions
--- a/1
+++ b/1
@ -96,7 +96,6 @@ formal:
 # Build Examples
 nexys_a7: nexys_a7_io_core_ether nexys_a7_io_core_uart nexys_a7_ps2_logic_analyzer nexys_a7_video_sprite_ether nexys_a7_video_sprite_uart

-
 nexys_a7_io_core_ether:
 	cd examples/nexys_a7/io_core_ether/;\
 	manta gen manta.yaml src/manta.v;		\
--- a/src/manta/uart_iface/uart_rx.v
+++ b/src/manta/uart_iface/uart_rx.v
@ -58,13 +58,7 @@ module uart_rx (
                end
            end
        end
-
-
-
-
-
-
    end
-
 endmodule
+
 `default_nettype wire
--- a/test/functional_sim/uart_tb/rx_uart.v
+++ b/test/functional_sim/uart_tb/rx_uart.v
--- a/test/functional_sim/uart_tb/tx_uart.v
+++ b/test/functional_sim/uart_tb/tx_uart.v
--- a/test/functional_sim/uart_tb/uart_tb.sv
+++ b/test/functional_sim/uart_tb/uart_tb.sv
--- a/test/functional_sim/uart_tb/uart_tx_tb.sv
+++ b/test/functional_sim/uart_tb/uart_tx_tb.sv