update MemoryCore references

src/manta/logic_analyzer/__init__.py

@@ -36,7 +36,8 @@ class LogicAnalyzerCore(Elaboratable):
             self._probes, self._fsm.get_max_addr() + 1, interface
         )
 
-        self._sample_mem = ReadOnlyMemoryCore(
+        self._sample_mem = MemoryCore(
+            mode = "fpga_to_host",
             width=sum(self._config["probes"].values()),
             depth=self._config["sample_depth"],
             base_addr=self._trig_blk.get_max_addr() + 1,
@@ -158,7 +159,7 @@ class LogicAnalyzerCore(Elaboratable):
         # Concat all the probes together, and feed to input of sample memory
         # (it is necessary to reverse the order such that first probe occupies
         # the lowest location in memory)
-        m.d.comb += self._sample_mem.user_data.eq(Cat(self._probes[::-1]))
+        m.d.comb += self._sample_mem.user_data_in.eq(Cat(self._probes[::-1]))
 
         # Wire bus connections between internal modules
         m.d.comb += [
@@ -170,7 +171,7 @@ class LogicAnalyzerCore(Elaboratable):
             # Non-bus Connections
             self._fsm.trigger.eq(self._trig_blk.trig),
             self._sample_mem.user_addr.eq(self._fsm.write_pointer),
-            self._sample_mem.user_we.eq(self._fsm.write_enable),
+            self._sample_mem.user_write_enable.eq(self._fsm.write_enable),
         ]
 
         return m

src/manta/manta.py

@@ -80,9 +80,8 @@ class Manta(Elaboratable):
 
     def _get_cores(self):
         """
-        Creates instances of the cores (IOCore, LogicAnalyzerCore,
-        ReadOnlyMemoryCore) specified in the user's configuration, and returns
-        them as a list.
+        Creates instances of the cores (IOCore, LogicAnalyzerCore, MemoryCore)
+        specified in the user's configuration, and returns them as a list.
         """
 
         self._cores = {}
@@ -95,7 +94,7 @@ class Manta(Elaboratable):
                 core = LogicAnalyzerCore(attrs, base_addr, self.interface)
 
             elif attrs["type"] == "memory_read_only":
-                core = ReadOnlyMemoryCore.from_config(attrs, base_addr, self.interface)
+                core = MemoryCore.from_config(attrs, base_addr, self.interface)
 
             # Make sure we're not out of address space
             if core.get_max_addr() > (2**16) - 1:

test/test_mem_core_hw.py

@@ -73,8 +73,8 @@ class MemoryCoreLoopbackTest(Elaboratable):
 
         m.d.comb += [
             self.manta.mem_core.user_addr.eq(addr),
-            self.manta.mem_core.user_data.eq(data),
-            self.manta.mem_core.user_we.eq(we),
+            self.manta.mem_core.user_data_in.eq(data),
+            self.manta.mem_core.user_write_enable.eq(we),
             self.manta.interface.rx.eq(uart_pins.rx.i),
             uart_pins.tx.o.eq(self.manta.interface.tx),
         ]