add simulate decorator
This commit is contained in:
Fischer Moseley
parent
2e2397013e
commit
e2d52a6e2d
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@ -22,8 +22,8 @@ class MemoryCore(Elaboratable):
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self._base_addr = base_addr
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self._interface = interface
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self._n_brams = ceil(self._width / 16)
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self._max_addr = self._base_addr + (self._depth * self._n_brams)
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self._n_mems = ceil(self._width / 16)
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self._max_addr = self._base_addr + (self._depth * self._n_mems)
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# Bus Connections
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self.bus_i = Signal(InternalBus())
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@ -106,23 +106,43 @@ class MemoryCore(Elaboratable):
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start_addr = self._base_addr + (i * self._depth)
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stop_addr = start_addr + self._depth - 1
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# Handle write ports
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if self._mode in ["host_to_fpga", "bidirectional"]:
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pass
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# write_port = mem.write_port()
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# m.d.sync += write_port.data.eq(self.bus_i.data)
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# m.d.sync += write_port.en.eq(self.bus_i.rw)
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# m.d.sync += write_port.addr.eq(self.bus_i.addr - start_addr)
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# # Handle write ports
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# if self._mode in ["host_to_fpga", "bidirectional"]:
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# write_port = mem.write_port()
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# m.d.sync += write_port.data.eq(self.bus_i.data)
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# m.d.sync += write_port.en.eq(self.bus_i.rw)
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# m.d.sync += write_port.addr.eq(self.bus_i.addr - start_addr)
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# Handle read ports
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if self._mode in ["fpga_to_host", "bidirectional"]:
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# # Handle read ports
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# if self._mode in ["fpga_to_host", "bidirectional"]:
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# read_port = mem.read_port()
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# m.d.comb += read_port.en.eq(1)
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# # Throw BRAM operations into the front of the pipeline
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# with m.If(
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# (self.bus_i.valid)
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# & (~self.bus_i.rw)
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# & (self.bus_i.addr >= start_addr)
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# & (self.bus_i.addr <= stop_addr)
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# ):
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# m.d.sync += read_port.addr.eq(self.bus_i.addr - start_addr)
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# # Pull BRAM reads from the back of the pipeline
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# with m.If(
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# (self._bus_pipe[2].valid)
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# & (~self._bus_pipe[2].rw)
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# & (self._bus_pipe[2].addr >= start_addr)
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# & (self._bus_pipe[2].addr <= stop_addr)
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# ):
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# m.d.sync += self.bus_o.data.eq(read_port.data)
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if self._mode == "fpga_to_host":
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read_port = mem.read_port()
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m.d.comb += read_port.en.eq(1)
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# Throw BRAM operations into the front of the pipeline
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with m.If(
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(self.bus_i.valid)
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& (~self.bus_i.rw)
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& (self.bus_i.addr >= start_addr)
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& (self.bus_i.addr <= stop_addr)
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):
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@ -137,6 +157,47 @@ class MemoryCore(Elaboratable):
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):
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m.d.sync += self.bus_o.data.eq(read_port.data)
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elif self._mode == "host_to_fpga":
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write_port = mem.write_port()
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m.d.sync += write_port.en.eq(0)
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# Throw BRAM operations into the front of the pipeline
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with m.If(
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(self.bus_i.valid)
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& (self.bus_i.addr >= start_addr)
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& (self.bus_i.addr <= stop_addr)
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):
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m.d.sync += write_port.addr.eq(self.bus_i.addr - start_addr)
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m.d.sync += write_port.data.eq(self.bus_i.data)
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m.d.sync += write_port.en.eq(self.bus_i.rw)
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elif self._mode == "bidirectional":
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read_port = mem.read_port()
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m.d.comb += read_port.en.eq(1)
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write_port = mem.write_port()
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m.d.sync += write_port.en.eq(0)
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# Throw BRAM operations into the front of the pipeline
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with m.If(
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(self.bus_i.valid)
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& (self.bus_i.addr >= start_addr)
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& (self.bus_i.addr <= stop_addr)
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):
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m.d.sync += read_port.addr.eq(self.bus_i.addr - start_addr)
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m.d.sync += write_port.addr.eq(self.bus_i.addr - start_addr)
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m.d.sync += write_port.data.eq(self.bus_i.data)
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m.d.sync += write_port.en.eq(self.bus_i.rw)
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# Pull BRAM reads from the back of the pipeline
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with m.If(
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(self._bus_pipe[2].valid)
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& (~self._bus_pipe[2].rw)
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& (self._bus_pipe[2].addr >= start_addr)
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& (self._bus_pipe[2].addr <= stop_addr)
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):
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m.d.sync += self.bus_o.data.eq(read_port.data)
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def _tie_mems_to_user_logic(self, m):
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# Handle write ports
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if self._mode in ["fpga_to_host", "bidirectional"]:
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@ -238,7 +299,7 @@ class MemoryCore(Elaboratable):
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bus_addrs = self._convert_user_to_bus_addr(addrs)
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datas = self._interface.read(bus_addrs)
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data_chunks = split_into_chunks(datas, self._n_brams)
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data_chunks = split_into_chunks(datas, self._n_mems)
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return [words_to_value(chunk) for chunk in data_chunks]
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def write(self, addrs, datas):
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@ -264,5 +325,5 @@ class MemoryCore(Elaboratable):
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raise TypeError("Write data must all be integers.")
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bus_addrs = self._convert_user_to_bus_addr([addrs])[0]
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bus_datas = [word for d in datas for word in value_to_words(d, self._n_brams)]
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bus_datas = [word for d in datas for word in value_to_words(d, self._n_mems)]
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self._interface.write(bus_addrs, bus_datas)
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@ -83,22 +83,41 @@ def split_into_chunks(data, chunk_size):
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return [data[i : i + chunk_size] for i in range(0, len(data), chunk_size)]
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def simulate(top, testbench, vcd_path=None):
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def simulate(top):
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"""
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Run a behavior simulation using Amaranth's built-in simulator `pysim`. Takes
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the top-level module to simulate, the testbench process to run, and an optional
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path to export a VCD file to.
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A decorator for running behavioral simulation using Amaranth's built-in
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simulator. Requires the top-level module in the simulation as an argument,
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and automatically names VCD file containing the waveform dump with the name
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of the function being decorated.
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"""
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sim = Simulator(top)
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sim.add_clock(1e-6) # 1 MHz
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sim.add_sync_process(testbench)
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if vcd_path is None:
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sim.run()
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def decorator(testbench):
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def wrapper(*args, **kwargs):
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sim = Simulator(top)
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sim.add_clock(1e-6) # 1 MHz
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sim.add_sync_process(testbench)
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else:
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with sim.write_vcd(vcd_path):
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sim.run()
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vcd_path = testbench.__name__ + ".vcd"
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with sim.write_vcd(vcd_path):
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sim.run()
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return wrapper
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return decorator
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# def simulate_decorator(testbench):
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# def wrapper_accepting_arguments(top):
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# sim = Simulator(top)
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# sim.add_clock(1e-6) # 1 MHz
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# sim.add_sync_process(testbench)
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# vcd_path = testbench.__name__ + ".vcd"
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# with sim.write_vcd(vcd_path):
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# sim.run()
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# return wrapper_accepting_arguments
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def verify_register(module, addr, expected_data):
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@ -143,7 +162,10 @@ def write_register(module, addr, data):
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yield module.bus_i.rw.eq(1)
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yield module.bus_i.valid.eq(1)
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yield
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yield module.bus_i.addr.eq(0)
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yield module.bus_i.data.eq(0)
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yield module.bus_i.valid.eq(0)
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yield module.bus_i.rw.eq(0)
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yield
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@ -86,35 +86,29 @@ def verify_bad_bytes(bytes):
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yield bridge_rx.valid_i.eq(0)
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@simulate(bridge_rx)
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def test_read_decode():
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def testbench():
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yield from verify_read_decoding(b"R0000\r\n", 0x0000)
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yield from verify_read_decoding(b"R1234\r\n", 0x1234)
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yield from verify_read_decoding(b"RBABE\r\n", 0xBABE)
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yield from verify_read_decoding(b"R5678\n", 0x5678)
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yield from verify_read_decoding(b"R9ABC\r", 0x9ABC)
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simulate(bridge_rx, testbench)
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yield from verify_read_decoding(b"R0000\r\n", 0x0000)
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yield from verify_read_decoding(b"R1234\r\n", 0x1234)
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yield from verify_read_decoding(b"RBABE\r\n", 0xBABE)
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yield from verify_read_decoding(b"R5678\n", 0x5678)
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yield from verify_read_decoding(b"R9ABC\r", 0x9ABC)
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@simulate(bridge_rx)
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def test_write_decode():
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def testbench():
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yield from verify_write_decoding(b"W12345678\r\n", 0x1234, 0x5678)
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yield from verify_write_decoding(b"WDEADBEEF\r\n", 0xDEAD, 0xBEEF)
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yield from verify_write_decoding(b"WDEADBEEF\r", 0xDEAD, 0xBEEF)
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yield from verify_write_decoding(b"WB0BACAFE\n", 0xB0BA, 0xCAFE)
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simulate(bridge_rx, testbench)
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yield from verify_write_decoding(b"W12345678\r\n", 0x1234, 0x5678)
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yield from verify_write_decoding(b"WDEADBEEF\r\n", 0xDEAD, 0xBEEF)
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yield from verify_write_decoding(b"WDEADBEEF\r", 0xDEAD, 0xBEEF)
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yield from verify_write_decoding(b"WB0BACAFE\n", 0xB0BA, 0xCAFE)
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@simulate(bridge_rx)
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def test_no_decode():
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def testbench():
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yield from verify_bad_bytes(b"RABC\r\n")
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yield from verify_bad_bytes(b"R12345\r\n")
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yield from verify_bad_bytes(b"M\r\n")
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yield from verify_bad_bytes(b"W123456789101112131415161718191201222\r\n")
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yield from verify_bad_bytes(b"RABCG\r\n")
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yield from verify_bad_bytes(b"WABC[]()##*@\r\n")
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yield from verify_bad_bytes(b"R\r\n")
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simulate(bridge_rx, testbench)
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yield from verify_bad_bytes(b"RABC\r\n")
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yield from verify_bad_bytes(b"R12345\r\n")
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yield from verify_bad_bytes(b"M\r\n")
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yield from verify_bad_bytes(b"W123456789101112131415161718191201222\r\n")
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yield from verify_bad_bytes(b"RABCG\r\n")
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yield from verify_bad_bytes(b"WABC[]()##*@\r\n")
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yield from verify_bad_bytes(b"R\r\n")
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@ -57,11 +57,9 @@ def verify_encoding(data, bytes):
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raise ValueError(f"Received {sent_bytes} instead of {bytes}.")
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@simulate(bridge_tx)
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def test_some_random_values():
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def testbench():
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for i in sample(range(0xFFFF), k=5000):
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expected = f"D{i:04X}\r\n".encode("ascii")
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print(i)
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yield from verify_encoding(i, expected)
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simulate(bridge_tx, testbench)
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for i in sample(range(0xFFFF), k=5000):
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expected = f"D{i:04X}\r\n".encode("ascii")
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print(i)
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yield from verify_encoding(i, expected)
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@ -26,92 +26,82 @@ def pulse_strobe_register():
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yield from write_register(io_core, strobe_addr, 0)
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@simulate(io_core)
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def test_input_probe_buffer_initial_value():
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def testbench():
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# Verify all input probe buffers initialize to zero
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for i in inputs:
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addrs = io_core._memory_map[i.name]["addrs"]
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# Verify all input probe buffers initialize to zero
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for i in inputs:
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addrs = io_core._memory_map[i.name]["addrs"]
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for addr in addrs:
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yield from verify_register(io_core, addr, 0)
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simulate(io_core, testbench)
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for addr in addrs:
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yield from verify_register(io_core, addr, 0)
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@simulate(io_core)
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def test_output_probe_buffer_initial_value():
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def testbench():
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# Verify all output probe buffers initialize to the values in the config
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for o in outputs:
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addrs = io_core._memory_map[o.name]["addrs"]
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datas = value_to_words(o.reset, len(addrs))
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# Verify all output probe buffers initialize to the values in the config
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for o in outputs:
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addrs = io_core._memory_map[o.name]["addrs"]
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datas = value_to_words(o.reset, len(addrs))
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for addr, data in zip(addrs, datas):
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yield from verify_register(io_core, addr, data)
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simulate(io_core, testbench)
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for addr, data in zip(addrs, datas):
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yield from verify_register(io_core, addr, data)
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@simulate(io_core)
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def test_output_probes_are_writeable():
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def testbench():
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for o in outputs:
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addrs = io_core._memory_map[o.name]["addrs"]
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test_value = randint(0, (2**o.width) - 1)
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datas = value_to_words(test_value, len(addrs))
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for o in outputs:
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addrs = io_core._memory_map[o.name]["addrs"]
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test_value = randint(0, (2**o.width) - 1)
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datas = value_to_words(test_value, len(addrs))
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# write value to registers
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for addr, data in zip(addrs, datas):
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yield from write_register(io_core, addr, data)
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# write value to registers
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for addr, data in zip(addrs, datas):
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yield from write_register(io_core, addr, data)
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# read value back from registers
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for addr, data in zip(addrs, datas):
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yield from verify_register(io_core, addr, data)
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simulate(io_core, testbench)
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# read value back from registers
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for addr, data in zip(addrs, datas):
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yield from verify_register(io_core, addr, data)
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@simulate(io_core)
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def test_output_probes_update():
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def testbench():
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for o in outputs:
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addrs = io_core._memory_map[o.name]["addrs"]
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test_value = randint(0, (2**o.width) - 1)
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datas = value_to_words(test_value, len(addrs))
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for o in outputs:
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addrs = io_core._memory_map[o.name]["addrs"]
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test_value = randint(0, (2**o.width) - 1)
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datas = value_to_words(test_value, len(addrs))
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# write value to registers
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for addr, data in zip(addrs, datas):
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yield from write_register(io_core, addr, data)
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# write value to registers
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for addr, data in zip(addrs, datas):
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yield from write_register(io_core, addr, data)
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# pulse strobe register
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yield from pulse_strobe_register()
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# pulse strobe register
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yield from pulse_strobe_register()
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# check that outputs took updated value
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value = yield (o)
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# check that outputs took updated value
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value = yield (o)
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if value != test_value:
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raise ValueError(
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f"Output probe {o.name} took value {value} instead of {test_value} after pulsing strobe."
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)
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if value != test_value:
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raise ValueError(
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f"Output probe {o.name} took value {value} instead of {test_value} after pulsing strobe."
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)
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else:
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print(f"Output probe {o.name} took value {value} after pulsing strobe.")
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simulate(io_core, testbench)
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else:
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print(f"Output probe {o.name} took value {value} after pulsing strobe.")
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@simulate(io_core)
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def test_input_probes_update():
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def testbench():
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for i in inputs:
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# set input probe value
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test_value = randint(0, (2**i.width) - 1)
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yield i.eq(test_value)
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for i in inputs:
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# set input probe value
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test_value = randint(0, (2**i.width) - 1)
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yield i.eq(test_value)
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# pulse strobe register
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yield from pulse_strobe_register()
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# pulse strobe register
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yield from pulse_strobe_register()
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# check that values are as expected once read back
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addrs = io_core._memory_map[i.name]["addrs"]
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datas = value_to_words(test_value, len(addrs))
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# check that values are as expected once read back
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addrs = io_core._memory_map[i.name]["addrs"]
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datas = value_to_words(test_value, len(addrs))
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for addr, data in zip(addrs, datas):
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yield from verify_register(io_core, addr, data)
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simulate(io_core, testbench)
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for addr, data in zip(addrs, datas):
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yield from verify_register(io_core, addr, data)
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|||
|
|
@ -6,244 +6,230 @@ config = {"sample_depth": 8}
|
|||
fsm = LogicAnalyzerFSM(config, base_addr=0, interface=None)
|
||||
|
||||
|
||||
@simulate(fsm)
|
||||
def test_signals_reset_correctly():
|
||||
def testbench():
|
||||
# Make sure pointers and write enable reset to zero
|
||||
for sig in [fsm.write_pointer, fsm.read_pointer, fsm.write_enable]:
|
||||
if (yield sig) != 0:
|
||||
raise ValueError
|
||||
|
||||
# Make sure state resets to IDLE
|
||||
if (yield fsm.state != States.IDLE):
|
||||
# Make sure pointers and write enable reset to zero
|
||||
for sig in [fsm.write_pointer, fsm.read_pointer, fsm.write_enable]:
|
||||
if (yield sig) != 0:
|
||||
raise ValueError
|
||||
|
||||
simulate(fsm, testbench)
|
||||
# Make sure state resets to IDLE
|
||||
if (yield fsm.state != States.IDLE):
|
||||
raise ValueError
|
||||
|
||||
|
||||
@simulate(fsm)
|
||||
def test_single_shot_no_wait_for_trigger():
|
||||
def testbench():
|
||||
# Configure and start FSM
|
||||
yield fsm.trigger.eq(1)
|
||||
yield fsm.trigger_mode.eq(TriggerModes.SINGLE_SHOT)
|
||||
yield fsm.trigger_location.eq(4)
|
||||
yield fsm.request_start.eq(1)
|
||||
# Configure and start FSM
|
||||
yield fsm.trigger.eq(1)
|
||||
yield fsm.trigger_mode.eq(TriggerModes.SINGLE_SHOT)
|
||||
yield fsm.trigger_location.eq(4)
|
||||
yield fsm.request_start.eq(1)
|
||||
|
||||
# Wait until write_enable is asserted
|
||||
while not (yield fsm.write_enable):
|
||||
yield
|
||||
|
||||
# Wait 8 clock cycles for capture to complete
|
||||
for i in range(8):
|
||||
# Make sure that read_pointer does not increase
|
||||
if (yield fsm.read_pointer) != 0:
|
||||
raise ValueError
|
||||
|
||||
# Make sure that write_pointer increases by one each cycle
|
||||
if (yield fsm.write_pointer) != i:
|
||||
raise ValueError
|
||||
|
||||
yield
|
||||
|
||||
# Wait one clock cycle (to let BRAM contents cycle in)
|
||||
# Wait until write_enable is asserted
|
||||
while not (yield fsm.write_enable):
|
||||
yield
|
||||
|
||||
# Check that write_pointer points to the end of memory
|
||||
if (yield fsm.write_pointer) != 7:
|
||||
# Wait 8 clock cycles for capture to complete
|
||||
for i in range(8):
|
||||
# Make sure that read_pointer does not increase
|
||||
if (yield fsm.read_pointer) != 0:
|
||||
raise ValueError
|
||||
|
||||
# Check that state is CAPTURED
|
||||
if (yield fsm.state) != States.CAPTURED:
|
||||
# Make sure that write_pointer increases by one each cycle
|
||||
if (yield fsm.write_pointer) != i:
|
||||
raise ValueError
|
||||
|
||||
simulate(fsm, testbench, "single_shot_no_wait_for_trigger.vcd")
|
||||
yield
|
||||
|
||||
# Wait one clock cycle (to let BRAM contents cycle in)
|
||||
yield
|
||||
|
||||
# Check that write_pointer points to the end of memory
|
||||
if (yield fsm.write_pointer) != 7:
|
||||
raise ValueError
|
||||
|
||||
# Check that state is CAPTURED
|
||||
if (yield fsm.state) != States.CAPTURED:
|
||||
raise ValueError
|
||||
|
||||
|
||||
@simulate(fsm)
|
||||
def test_single_shot_wait_for_trigger():
|
||||
def testbench():
|
||||
# Configure and start FSM
|
||||
yield fsm.trigger_mode.eq(TriggerModes.SINGLE_SHOT)
|
||||
yield fsm.trigger_location.eq(4)
|
||||
yield fsm.request_start.eq(1)
|
||||
yield
|
||||
yield
|
||||
# Configure and start FSM
|
||||
yield fsm.trigger_mode.eq(TriggerModes.SINGLE_SHOT)
|
||||
yield fsm.trigger_location.eq(4)
|
||||
yield fsm.request_start.eq(1)
|
||||
yield
|
||||
yield
|
||||
|
||||
# Check that write_enable is asserted a cycle after request_start
|
||||
if not (yield fsm.write_enable):
|
||||
raise ValueError
|
||||
# Check that write_enable is asserted a cycle after request_start
|
||||
if not (yield fsm.write_enable):
|
||||
raise ValueError
|
||||
|
||||
# Wait 4 clock cycles to get to IN_POSITION
|
||||
for i in range(4):
|
||||
rp = yield fsm.read_pointer
|
||||
wp = yield fsm.write_pointer
|
||||
|
||||
# Make sure that read_pointer does not increase
|
||||
if rp != 0:
|
||||
raise ValueError
|
||||
|
||||
# Make sure that write_pointer increases by one each cycle
|
||||
if wp != i:
|
||||
raise ValueError
|
||||
|
||||
yield
|
||||
|
||||
# Wait a few cycles before triggering
|
||||
for _ in range(10):
|
||||
yield
|
||||
|
||||
# Provide the trigger, and check that the capture completes 4 cycles later
|
||||
yield fsm.trigger.eq(1)
|
||||
yield
|
||||
|
||||
for i in range(4):
|
||||
yield
|
||||
|
||||
# Wait one clock cycle (to let BRAM contents cycle in)
|
||||
yield
|
||||
|
||||
# Check that write_pointer points to the end of memory
|
||||
# Wait 4 clock cycles to get to IN_POSITION
|
||||
for i in range(4):
|
||||
rp = yield fsm.read_pointer
|
||||
wp = yield fsm.write_pointer
|
||||
if (wp + 1) % config["sample_depth"] != rp:
|
||||
raise ValueError
|
||||
|
||||
# Check that state is CAPTURED
|
||||
if (yield fsm.state) != States.CAPTURED:
|
||||
raise ValueError
|
||||
|
||||
simulate(fsm, testbench, "single_shot_wait_for_trigger.vcd")
|
||||
|
||||
|
||||
def test_immediate():
|
||||
def testbench():
|
||||
# Configure and start FSM
|
||||
yield fsm.trigger_mode.eq(TriggerModes.IMMEDIATE)
|
||||
yield fsm.request_start.eq(1)
|
||||
yield
|
||||
yield
|
||||
|
||||
# Check that write_enable is asserted a cycle after request_start
|
||||
if not (yield fsm.write_enable):
|
||||
raise ValueError
|
||||
|
||||
for i in range(config["sample_depth"]):
|
||||
rp = yield fsm.read_pointer
|
||||
wp = yield fsm.write_pointer
|
||||
|
||||
if rp != 0:
|
||||
raise ValueError
|
||||
|
||||
if wp != i:
|
||||
raise ValueError
|
||||
|
||||
yield
|
||||
|
||||
# Wait one clock cycle (to let BRAM contents cycle in)
|
||||
yield
|
||||
|
||||
# Check that write_pointer points to the end of memory
|
||||
rp = yield fsm.read_pointer
|
||||
wp = yield fsm.write_pointer
|
||||
# Make sure that read_pointer does not increase
|
||||
if rp != 0:
|
||||
raise ValueError
|
||||
if wp != 7:
|
||||
|
||||
# Make sure that write_pointer increases by one each cycle
|
||||
if wp != i:
|
||||
raise ValueError
|
||||
|
||||
# Check that state is CAPTURED
|
||||
if (yield fsm.state) != States.CAPTURED:
|
||||
yield
|
||||
|
||||
# Wait a few cycles before triggering
|
||||
for _ in range(10):
|
||||
yield
|
||||
|
||||
# Provide the trigger, and check that the capture completes 4 cycles later
|
||||
yield fsm.trigger.eq(1)
|
||||
yield
|
||||
|
||||
for i in range(4):
|
||||
yield
|
||||
|
||||
# Wait one clock cycle (to let BRAM contents cycle in)
|
||||
yield
|
||||
|
||||
# Check that write_pointer points to the end of memory
|
||||
rp = yield fsm.read_pointer
|
||||
wp = yield fsm.write_pointer
|
||||
if (wp + 1) % config["sample_depth"] != rp:
|
||||
raise ValueError
|
||||
|
||||
# Check that state is CAPTURED
|
||||
if (yield fsm.state) != States.CAPTURED:
|
||||
raise ValueError
|
||||
|
||||
|
||||
@simulate(fsm)
|
||||
def test_immediate():
|
||||
# Configure and start FSM
|
||||
yield fsm.trigger_mode.eq(TriggerModes.IMMEDIATE)
|
||||
yield fsm.request_start.eq(1)
|
||||
yield
|
||||
yield
|
||||
|
||||
# Check that write_enable is asserted a cycle after request_start
|
||||
if not (yield fsm.write_enable):
|
||||
raise ValueError
|
||||
|
||||
for i in range(config["sample_depth"]):
|
||||
rp = yield fsm.read_pointer
|
||||
wp = yield fsm.write_pointer
|
||||
|
||||
if rp != 0:
|
||||
raise ValueError
|
||||
|
||||
simulate(fsm, testbench, "immediate.vcd")
|
||||
if wp != i:
|
||||
raise ValueError
|
||||
|
||||
yield
|
||||
|
||||
# Wait one clock cycle (to let BRAM contents cycle in)
|
||||
yield
|
||||
|
||||
# Check that write_pointer points to the end of memory
|
||||
rp = yield fsm.read_pointer
|
||||
wp = yield fsm.write_pointer
|
||||
if rp != 0:
|
||||
raise ValueError
|
||||
if wp != 7:
|
||||
raise ValueError
|
||||
|
||||
# Check that state is CAPTURED
|
||||
if (yield fsm.state) != States.CAPTURED:
|
||||
raise ValueError
|
||||
|
||||
|
||||
@simulate(fsm)
|
||||
def test_incremental():
|
||||
def testbench():
|
||||
# Configure and start FSM
|
||||
yield fsm.trigger_mode.eq(TriggerModes.INCREMENTAL)
|
||||
yield fsm.request_start.eq(1)
|
||||
yield
|
||||
yield
|
||||
# Configure and start FSM
|
||||
yield fsm.trigger_mode.eq(TriggerModes.INCREMENTAL)
|
||||
yield fsm.request_start.eq(1)
|
||||
yield
|
||||
yield
|
||||
|
||||
# Check that write_enable is asserted on the same edge as request_start
|
||||
if not (yield fsm.write_enable):
|
||||
raise ValueError
|
||||
|
||||
for _ in range(10):
|
||||
for _ in range(3):
|
||||
yield
|
||||
|
||||
yield fsm.trigger.eq(1)
|
||||
yield
|
||||
yield fsm.trigger.eq(0)
|
||||
yield
|
||||
|
||||
# Check that state is CAPTURED
|
||||
if (yield fsm.state) != States.CAPTURED:
|
||||
raise ValueError
|
||||
|
||||
simulate(fsm, testbench, "incremental.vcd")
|
||||
|
||||
|
||||
def test_single_shot_write_enable():
|
||||
def testbench():
|
||||
# Configure FSM
|
||||
yield fsm.trigger_mode.eq(TriggerModes.SINGLE_SHOT)
|
||||
yield fsm.trigger_location.eq(4)
|
||||
yield
|
||||
|
||||
# Make sure write is not enabled before starting the FSM
|
||||
if (yield fsm.write_enable):
|
||||
raise ValueError
|
||||
|
||||
# Start the FSM, ensure write enable is asserted throughout the capture
|
||||
yield fsm.request_start.eq(1)
|
||||
yield
|
||||
yield
|
||||
|
||||
for _ in range(config["sample_depth"]):
|
||||
if not (yield fsm.write_enable):
|
||||
raise ValueError
|
||||
# Check that write_enable is asserted on the same edge as request_start
|
||||
if not (yield fsm.write_enable):
|
||||
raise ValueError
|
||||
|
||||
for _ in range(10):
|
||||
for _ in range(3):
|
||||
yield
|
||||
|
||||
yield fsm.trigger.eq(1)
|
||||
yield
|
||||
yield fsm.trigger.eq(0)
|
||||
yield
|
||||
|
||||
for _ in range(4):
|
||||
if not (yield fsm.write_enable):
|
||||
raise ValueError
|
||||
# Check that state is CAPTURED
|
||||
if (yield fsm.state) != States.CAPTURED:
|
||||
raise ValueError
|
||||
|
||||
yield
|
||||
|
||||
# Make sure write_enable is deasserted after
|
||||
if (yield fsm.write_enable):
|
||||
@simulate(fsm)
|
||||
def test_single_shot_write_enable():
|
||||
# Configure FSM
|
||||
yield fsm.trigger_mode.eq(TriggerModes.SINGLE_SHOT)
|
||||
yield fsm.trigger_location.eq(4)
|
||||
yield
|
||||
|
||||
# Make sure write is not enabled before starting the FSM
|
||||
if (yield fsm.write_enable):
|
||||
raise ValueError
|
||||
|
||||
# Start the FSM, ensure write enable is asserted throughout the capture
|
||||
yield fsm.request_start.eq(1)
|
||||
yield
|
||||
yield
|
||||
|
||||
for _ in range(config["sample_depth"]):
|
||||
if not (yield fsm.write_enable):
|
||||
raise ValueError
|
||||
|
||||
simulate(fsm, testbench, "single_shot_write_enable.vcd")
|
||||
yield
|
||||
|
||||
yield fsm.trigger.eq(1)
|
||||
yield
|
||||
|
||||
for _ in range(4):
|
||||
if not (yield fsm.write_enable):
|
||||
raise ValueError
|
||||
|
||||
yield
|
||||
|
||||
# Make sure write_enable is deasserted after
|
||||
if (yield fsm.write_enable):
|
||||
raise ValueError
|
||||
|
||||
|
||||
@simulate(fsm)
|
||||
def test_immediate_write_enable():
|
||||
def testbench():
|
||||
# Configure FSM
|
||||
yield fsm.trigger_mode.eq(TriggerModes.IMMEDIATE)
|
||||
yield
|
||||
# Configure FSM
|
||||
yield fsm.trigger_mode.eq(TriggerModes.IMMEDIATE)
|
||||
yield
|
||||
|
||||
# Make sure write is not enabled before starting the FSM
|
||||
if (yield fsm.write_enable):
|
||||
# Make sure write is not enabled before starting the FSM
|
||||
if (yield fsm.write_enable):
|
||||
raise ValueError
|
||||
|
||||
# Start the FSM, ensure write enable is asserted throughout the capture
|
||||
yield fsm.request_start.eq(1)
|
||||
yield
|
||||
yield
|
||||
|
||||
for _ in range(config["sample_depth"]):
|
||||
if not (yield fsm.write_enable):
|
||||
raise ValueError
|
||||
|
||||
# Start the FSM, ensure write enable is asserted throughout the capture
|
||||
yield fsm.request_start.eq(1)
|
||||
yield
|
||||
yield
|
||||
|
||||
for _ in range(config["sample_depth"]):
|
||||
if not (yield fsm.write_enable):
|
||||
raise ValueError
|
||||
|
||||
yield
|
||||
|
||||
# Make sure write_enable is deasserted after
|
||||
if (yield fsm.write_enable):
|
||||
raise ValueError
|
||||
|
||||
simulate(fsm, testbench, "immediate_write_enable.vcd")
|
||||
# Make sure write_enable is deasserted after
|
||||
if (yield fsm.write_enable):
|
||||
raise ValueError
|
||||
|
|
|
|||
|
|
@ -61,42 +61,40 @@ def set_probe(name, value):
|
|||
yield probe.eq(value)
|
||||
|
||||
|
||||
@simulate(la)
|
||||
def test_single_shot_capture():
|
||||
def testbench():
|
||||
# # ok nice what happens if we try to run the core, which includes:
|
||||
yield from set_fsm_register("request_stop", 1)
|
||||
yield from set_fsm_register("request_stop", 0)
|
||||
# # ok nice what happens if we try to run the core, which includes:
|
||||
yield from set_fsm_register("request_stop", 1)
|
||||
yield from set_fsm_register("request_stop", 0)
|
||||
|
||||
# setting triggers
|
||||
yield from set_trig_blk_register("curly_op", Operations.EQ)
|
||||
yield from set_trig_blk_register("curly_arg", 4)
|
||||
# setting triggers
|
||||
yield from set_trig_blk_register("curly_op", Operations.EQ)
|
||||
yield from set_trig_blk_register("curly_arg", 4)
|
||||
|
||||
# setting trigger mode
|
||||
yield from set_fsm_register("trigger_mode", 0)
|
||||
# setting trigger mode
|
||||
yield from set_fsm_register("trigger_mode", 0)
|
||||
|
||||
# setting trigger location
|
||||
yield from set_fsm_register("trigger_location", 511)
|
||||
# setting trigger location
|
||||
yield from set_fsm_register("trigger_location", 511)
|
||||
|
||||
# starting capture
|
||||
yield from set_fsm_register("request_start", 1)
|
||||
yield from set_fsm_register("request_start", 0)
|
||||
# starting capture
|
||||
yield from set_fsm_register("request_start", 1)
|
||||
yield from set_fsm_register("request_start", 0)
|
||||
|
||||
# wait a few hundred clock cycles, see what happens
|
||||
for _ in range(700):
|
||||
yield
|
||||
# wait a few hundred clock cycles, see what happens
|
||||
for _ in range(700):
|
||||
yield
|
||||
|
||||
# provide the trigger condition
|
||||
yield from set_probe("curly", 4)
|
||||
# provide the trigger condition
|
||||
yield from set_probe("curly", 4)
|
||||
|
||||
for _ in range(700):
|
||||
yield
|
||||
for _ in range(700):
|
||||
yield
|
||||
|
||||
# dump sample memory contents
|
||||
yield from write_register(la, 0, 0)
|
||||
yield from write_register(la, 0, 1)
|
||||
yield from write_register(la, 0, 0)
|
||||
# dump sample memory contents
|
||||
yield from write_register(la, 0, 0)
|
||||
yield from write_register(la, 0, 1)
|
||||
yield from write_register(la, 0, 0)
|
||||
|
||||
for addr in range(la.get_max_addr()):
|
||||
yield from print_data_at_addr(addr)
|
||||
|
||||
simulate(la, testbench, "la_core.vcd")
|
||||
for addr in range(la.get_max_addr()):
|
||||
yield from print_data_at_addr(addr)
|
||||
|
|
|
|||
|
|
@ -1,44 +1,158 @@
|
|||
from manta.memory_core import MemoryCore
|
||||
from manta.utils import *
|
||||
from random import randint, sample
|
||||
from random import randint, sample, choice
|
||||
|
||||
width = 18
|
||||
depth = 512
|
||||
base_addr = 0
|
||||
mem_core = MemoryCore(
|
||||
mode="bidirectional", width=width, depth=depth, base_addr=base_addr, interface=None
|
||||
)
|
||||
|
||||
max_addr = mem_core.get_max_addr()
|
||||
bus_addrs = list(range(base_addr, max_addr)) # include the endpoint!
|
||||
user_addrs = list(range(depth))
|
||||
|
||||
|
||||
def fill_mem_from_user_port(mem_core, depth):
|
||||
for i in range(depth):
|
||||
yield mem_core.user_addr.eq(i)
|
||||
yield mem_core.user_data_in.eq(i)
|
||||
yield mem_core.user_write_enable.eq(1)
|
||||
@simulate(mem_core)
|
||||
def test_bidirectional():
|
||||
# make sure each address on the bus side contains zero
|
||||
for addr in bus_addrs:
|
||||
yield from verify_register(mem_core, addr, 0)
|
||||
|
||||
# make sure each address on the user side contains zero
|
||||
for addr in user_addrs:
|
||||
yield from verify_user_side(mem_core, addr, 0)
|
||||
|
||||
# write then immediately read
|
||||
for addr in bus_addrs:
|
||||
# this part is a little hard to check since we might have a
|
||||
# memory at the end of the address space that's less than
|
||||
# 16-bits wide. so we'll have to calculate how wide our
|
||||
# memory is
|
||||
|
||||
n_full = width // 16
|
||||
if addr < base_addr + (n_full * depth):
|
||||
data_width = 16
|
||||
else:
|
||||
data_width = width % 16
|
||||
|
||||
data = randint(0, (2**data_width) - 1)
|
||||
yield from write_register(mem_core, addr, data)
|
||||
yield
|
||||
yield
|
||||
yield
|
||||
yield
|
||||
yield from verify_register(mem_core, addr, data)
|
||||
yield
|
||||
yield
|
||||
yield
|
||||
yield
|
||||
yield
|
||||
|
||||
# write-write-write then read-read-read
|
||||
model = {}
|
||||
for addr in sample(bus_addrs, len(bus_addrs)):
|
||||
n_full = width // 16
|
||||
if addr < base_addr + (n_full * depth):
|
||||
data_width = 16
|
||||
else:
|
||||
data_width = width % 16
|
||||
|
||||
data = randint(0, (2**data_width) - 1)
|
||||
model[addr] = data
|
||||
yield from write_register(mem_core, addr, data)
|
||||
yield
|
||||
yield
|
||||
yield
|
||||
yield
|
||||
|
||||
for addr in sample(bus_addrs, len(bus_addrs)):
|
||||
yield from verify_register(mem_core, addr, model[addr])
|
||||
yield
|
||||
yield
|
||||
yield
|
||||
yield
|
||||
|
||||
# random reads and writes in random orders
|
||||
for _ in range(5):
|
||||
for addr in sample(bus_addrs, len(bus_addrs)):
|
||||
|
||||
operation = choice(["read", "write"])
|
||||
if operation == "read":
|
||||
yield from verify_register(mem_core, addr, model[addr])
|
||||
yield
|
||||
yield
|
||||
yield
|
||||
yield
|
||||
yield
|
||||
yield
|
||||
|
||||
elif operation == "write":
|
||||
n_full = width // 16
|
||||
|
||||
if addr < base_addr + (n_full * depth):
|
||||
data_width = 16
|
||||
else:
|
||||
data_width = width % 16
|
||||
|
||||
data = randint(0, (2**data_width) - 1)
|
||||
model[addr] = data
|
||||
|
||||
yield from write_register(mem_core, addr, data)
|
||||
yield
|
||||
yield
|
||||
yield
|
||||
yield
|
||||
yield
|
||||
yield
|
||||
|
||||
|
||||
def verify_user_side(mem_core, addr, expected_data):
|
||||
yield mem_core.user_addr.eq(addr)
|
||||
yield mem_core.user_write_enable.eq(0)
|
||||
yield
|
||||
|
||||
|
||||
def verify_mem_core(width, depth, base_addr):
|
||||
mem_core = MemoryCore("fpga_to_host", width, depth, base_addr, interface=None)
|
||||
|
||||
def testbench():
|
||||
yield from fill_mem_from_user_port(mem_core, depth)
|
||||
|
||||
# Read from address sequentially
|
||||
for i in range(depth):
|
||||
yield from verify_register(mem_core, i + base_addr, i % (2**width))
|
||||
|
||||
# Read from addresses randomly
|
||||
for i in sample(range(depth), k=depth):
|
||||
yield from verify_register(mem_core, i + base_addr, i % (2**width))
|
||||
|
||||
simulate(mem_core, testbench)
|
||||
data = yield (mem_core.user_data_out)
|
||||
if data != expected_data:
|
||||
raise ValueError(f"Read from {addr} yielded {data} instead of {expected_data}")
|
||||
|
||||
|
||||
def test_sweep_core_widths():
|
||||
for i in range(1, 64):
|
||||
verify_mem_core(i, 128, 0)
|
||||
# def fill_mem_from_user_port(mem_core, depth):
|
||||
# for i in range(depth):
|
||||
# yield mem_core.user_addr.eq(i)
|
||||
# yield mem_core.user_data_in.eq(i)
|
||||
# yield mem_core.user_write_enable.eq(1)
|
||||
# yield
|
||||
|
||||
# yield mem_core.user_write_enable.eq(0)
|
||||
# yield
|
||||
|
||||
|
||||
def test_random_cores():
|
||||
for _ in range(5):
|
||||
width = randint(0, 512)
|
||||
depth = randint(0, 1024)
|
||||
base_addr = randint(0, 2**16 - 1 - depth)
|
||||
verify_mem_core(width, depth, base_addr)
|
||||
# def verify_mem_core(width, depth, base_addr):
|
||||
# mem_core = MemoryCore("bidirectional", width, depth, base_addr, interface=None)
|
||||
|
||||
# def testbench():
|
||||
# yield from fill_mem_from_user_port(mem_core, depth)
|
||||
|
||||
# # Read from address sequentially
|
||||
# for i in range(depth):
|
||||
# yield from verify_register(mem_core, i + base_addr, i % (2**width))
|
||||
|
||||
# # Read from addresses randomly
|
||||
# for i in sample(range(depth), k=depth):
|
||||
# yield from verify_register(mem_core, i + base_addr, i % (2**width))
|
||||
|
||||
# simulate(mem_core, testbench)
|
||||
|
||||
# def test_sweep_core_widths():
|
||||
# for i in range(1, 64):
|
||||
# verify_mem_core(i, 128, 0)
|
||||
|
||||
|
||||
# def test_random_cores():
|
||||
# for _ in range(5):
|
||||
# width = randint(0, 512)
|
||||
# depth = randint(0, 1024)
|
||||
# base_addr = randint(0, 2**16 - 1 - depth)
|
||||
# verify_mem_core(width, depth, base_addr)
|
||||
|
|
|
|||
|
|
@ -6,34 +6,32 @@ from manta.utils import *
|
|||
source_bridge = UDPSourceBridge()
|
||||
|
||||
|
||||
@simulate(source_bridge)
|
||||
def test_normie_ops():
|
||||
def testbench():
|
||||
yield source_bridge.data_i.eq(0)
|
||||
yield source_bridge.last_i.eq(0)
|
||||
yield source_bridge.valid_i.eq(0)
|
||||
yield
|
||||
yield
|
||||
yield source_bridge.data_i.eq(0)
|
||||
yield source_bridge.last_i.eq(0)
|
||||
yield source_bridge.valid_i.eq(0)
|
||||
yield
|
||||
yield
|
||||
|
||||
yield source_bridge.data_i.eq(0x0000_0001)
|
||||
yield source_bridge.valid_i.eq(1)
|
||||
yield
|
||||
yield source_bridge.data_i.eq(0x1234_5678)
|
||||
yield
|
||||
yield source_bridge.valid_i.eq(0)
|
||||
yield
|
||||
yield
|
||||
yield source_bridge.data_i.eq(0x0000_0001)
|
||||
yield source_bridge.valid_i.eq(1)
|
||||
yield
|
||||
yield source_bridge.data_i.eq(0x1234_5678)
|
||||
yield
|
||||
yield source_bridge.valid_i.eq(0)
|
||||
yield
|
||||
yield
|
||||
|
||||
yield source_bridge.valid_i.eq(1)
|
||||
yield source_bridge.data_i.eq(0x0000_0001)
|
||||
yield
|
||||
yield source_bridge.data_i.eq(0x90AB_CDEF)
|
||||
yield
|
||||
yield source_bridge.data_i.eq(0x0000_0000)
|
||||
yield
|
||||
yield source_bridge.data_i.eq(0x1234_5678)
|
||||
yield
|
||||
yield source_bridge.valid_i.eq(0)
|
||||
yield
|
||||
yield
|
||||
|
||||
simulate(source_bridge, testbench, "source_bridge.vcd")
|
||||
yield source_bridge.valid_i.eq(1)
|
||||
yield source_bridge.data_i.eq(0x0000_0001)
|
||||
yield
|
||||
yield source_bridge.data_i.eq(0x90AB_CDEF)
|
||||
yield
|
||||
yield source_bridge.data_i.eq(0x0000_0000)
|
||||
yield
|
||||
yield source_bridge.data_i.eq(0x1234_5678)
|
||||
yield
|
||||
yield source_bridge.valid_i.eq(0)
|
||||
yield
|
||||
yield
|
||||
|
|
|
|||
|
|
@ -43,23 +43,19 @@ def verify_receive(data):
|
|||
raise ValueError("Failed to assert valid!")
|
||||
|
||||
|
||||
@simulate(uart_rx)
|
||||
def test_all_possible_bytes():
|
||||
def testbench():
|
||||
yield uart_rx.rx.eq(1)
|
||||
yield
|
||||
yield uart_rx.rx.eq(1)
|
||||
yield
|
||||
|
||||
for i in range(0xFF):
|
||||
yield from verify_receive(i)
|
||||
|
||||
simulate(uart_rx, testbench)
|
||||
for i in range(0xFF):
|
||||
yield from verify_receive(i)
|
||||
|
||||
|
||||
@simulate(uart_rx)
|
||||
def test_bytes_random_sample():
|
||||
def testbench():
|
||||
yield uart_rx.rx.eq(1)
|
||||
yield
|
||||
yield uart_rx.rx.eq(1)
|
||||
yield
|
||||
|
||||
for i in sample(range(0xFF), k=0xFF):
|
||||
yield from verify_receive(i)
|
||||
|
||||
simulate(uart_rx, testbench)
|
||||
for i in sample(range(0xFF), k=0xFF):
|
||||
yield from verify_receive(i)
|
||||
|
|
|
|||
|
|
@ -41,17 +41,13 @@ def verify_bit_sequence(byte):
|
|||
raise ValueError("Done not asserted at end of transmission!")
|
||||
|
||||
|
||||
@simulate(uart_tx)
|
||||
def test_all_possible_bytes():
|
||||
def testbench():
|
||||
for i in range(0xFF):
|
||||
yield from verify_bit_sequence(i)
|
||||
|
||||
simulate(uart_tx, testbench)
|
||||
for i in range(0xFF):
|
||||
yield from verify_bit_sequence(i)
|
||||
|
||||
|
||||
@simulate(uart_tx)
|
||||
def test_bytes_random_sample():
|
||||
def testbench():
|
||||
for i in sample(range(0xFF), k=0xFF):
|
||||
yield from verify_bit_sequence(i)
|
||||
|
||||
simulate(uart_tx, testbench)
|
||||
for i in sample(range(0xFF), k=0xFF):
|
||||
yield from verify_bit_sequence(i)
|
||||
|
|
|
|||
Loading…
Reference in New Issue