switch to wiring.Component instead of Elaboratable

src/manta/ethernet/__init__.py

@@ -1,4 +1,6 @@
 from amaranth import *
+from amaranth.lib import wiring
+from amaranth.lib.wiring import In, Out
 from manta.utils import *
 from manta.ethernet.source_bridge import UDPSourceBridge
 from manta.ethernet.sink_bridge import UDPSinkBridge
@@ -6,7 +8,7 @@ from random import randint
 import socket
 
 
-class EthernetInterface(Elaboratable):
+class EthernetInterface(wiring.Component):
     """
     A module for communicating with Manta over Ethernet, using UDP.
 

src/manta/ethernet/sink_bridge.py

@@ -1,8 +1,10 @@
 from amaranth import *
+from amaranth.lib import wiring
+from amaranth.lib.wiring import In, Out
 from manta.utils import *
 
 
-class UDPSinkBridge(Elaboratable):
+class UDPSinkBridge(wiring.Component):
     """
     A module for bridging Manta's internal bus to an AXI stream of UDP packet
     data. Connects to the LiteEth core's "sink" port.

src/manta/ethernet/source_bridge.py

@@ -1,8 +1,10 @@
 from amaranth import *
+from amaranth.lib import wiring
+from amaranth.lib.wiring import In, Out
 from manta.utils import *
 
 
-class UDPSourceBridge(Elaboratable):
+class UDPSourceBridge(wiring.Component):
     """
     A module for bridging the AXI-stream of incoming UDP packet data to Manta's
     internal bus. Connects to the LiteEth core's "source" port.

src/manta/logic_analyzer/__init__.py

@@ -1,4 +1,6 @@
 from amaranth import *
+from amaranth.lib import wiring
+from amaranth.lib.wiring import In, Out
 from manta.utils import *
 from manta.memory_core import MemoryCore
 from manta.logic_analyzer.trigger_block import LogicAnalyzerTriggerBlock

src/manta/logic_analyzer/fsm.py

@@ -1,6 +1,7 @@
 from amaranth import *
+from amaranth.lib import wiring
+from amaranth.lib.wiring import In, Out
 from amaranth.lib.enum import IntEnum
-from math import ceil, log2
 from manta.io_core import IOCore
 
 
@@ -18,7 +19,7 @@ class TriggerModes(IntEnum):
     IMMEDIATE = 2
 
 
-class LogicAnalyzerFSM(Elaboratable):
+class LogicAnalyzerFSM(wiring.Component):
     """
     A module containing the state machine for a LogicAnalyzerCore. Primarily
     responsible for controlling the write port of the Logic Analyzer's sample

src/manta/logic_analyzer/playback.py

@@ -1,7 +1,9 @@
 from amaranth import *
+from amaranth.lib import wiring
+from amaranth.lib.wiring import In, Out
 
 
-class LogicAnalyzerPlayback(Elaboratable):
+class LogicAnalyzerPlayback(wiring.Component):
     """
     A synthesizable module that plays back data captured by a
     LogicAnalyzerCore. Takes a list of all the samples captured by a core,

src/manta/logic_analyzer/trigger_block.py

@@ -1,9 +1,11 @@
 from amaranth import *
+from amaranth.lib import wiring
+from amaranth.lib.wiring import In, Out
 from amaranth.lib.enum import IntEnum
 from manta.io_core import IOCore
 
 
-class LogicAnalyzerTriggerBlock(Elaboratable):
+class LogicAnalyzerTriggerBlock(wiring.Component):
     """
     A module containing an instance of a LogicAnalyzerTrigger for each input
     probe. The operations and arguments of these LogicAnalyzerTriggers are set
@@ -86,7 +88,7 @@ class Operations(IntEnum):
     NEQ = 9
 
 
-class LogicAnalyzerTrigger(Elaboratable):
+class LogicAnalyzerTrigger(wiring.Component):
     """
     A module containing a programmable "trigger" for a given input signal,
     which asserts its output when the programmed "trigger condition" is met.

src/manta/manta.py

@@ -1,13 +1,14 @@
 from amaranth import *
+from amaranth.lib import wiring
+from amaranth.lib.wiring import In, Out
 from manta.uart import UARTInterface
-
 from manta.ethernet import EthernetInterface
 from manta.io_core import IOCore
 from manta.memory_core import MemoryCore
 from manta.logic_analyzer import LogicAnalyzerCore
 
 
-class Manta(Elaboratable):
+class Manta(wiring.Component):
     def __init__(self, config):
         # Load config from either a configuration file or a dictionary.
         # Users primarily use the config file, but the dictionary is
@@ -157,7 +158,7 @@ class Manta(Elaboratable):
         ports = self.interface.get_top_level_ports()
 
         for name, instance in self._cores.items():
-            ports += instance.get_top_level_ports()
+            ports += instance.top_level_ports
 
         return ports
 

src/manta/memory_core.py

@@ -1,4 +1,6 @@
 from amaranth import *
+from amaranth.lib import wiring
+from amaranth.lib.wiring import In, Out
 from manta.utils import *
 from math import ceil
 

src/manta/uart/__init__.py

@@ -1,4 +1,6 @@
 from amaranth import *
+from amaranth.lib import wiring
+from amaranth.lib.wiring import In, Out
 from manta.utils import *
 from manta.uart.receiver import UARTReceiver
 from manta.uart.receive_bridge import ReceiveBridge
@@ -7,7 +9,7 @@ from manta.uart.transmit_bridge import TransmitBridge
 from serial import Serial
 
 
-class UARTInterface(Elaboratable):
+class UARTInterface(wiring.Component):
     """
     A module for communicating with Manta over UART.
 

src/manta/uart/receive_bridge.py

@@ -1,4 +1,6 @@
 from amaranth import *
+from amaranth.lib import wiring
+from amaranth.lib.wiring import In, Out
 from amaranth.lib.enum import IntEnum
 from amaranth.lib.data import ArrayLayout
 
@@ -9,7 +11,7 @@ class States(IntEnum):
     WRITE = 2
 
 
-class ReceiveBridge(Elaboratable):
+class ReceiveBridge(wiring.Component):
     """
     A module for bridging the stream of bytes from the UARTReceiver module to
     Manta's internal bus.

src/manta/uart/receiver.py

@@ -1,7 +1,9 @@
 from amaranth import *
+from amaranth.lib import wiring
+from amaranth.lib.wiring import In, Out
 
 
-class UARTReceiver(Elaboratable):
+class UARTReceiver(wiring.Component):
     """
     A module for receiving bytes on a 8N1 UART at a configurable baudrate.
     Outputs bytes as a stream.

src/manta/uart/transmit_bridge.py

@@ -1,7 +1,9 @@
 from amaranth import *
+from amaranth.lib import wiring
+from amaranth.lib.wiring import In, Out
 
 
-class TransmitBridge(Elaboratable):
+class TransmitBridge(wiring.Component):
     """
     A module for bridging Manta's internal bus to the stream of bytes expected
     by the UARTTransmitter module.

src/manta/uart/transmitter.py

@@ -1,7 +1,9 @@
 from amaranth import *
+from amaranth.lib import wiring
+from amaranth.lib.wiring import In, Out
 
 
-class UARTTransmitter(Elaboratable):
+class UARTTransmitter(wiring.Component):
     """
     A module for transmitting bytes on a 8N1 UART at a configurable baudrate.
     Accepts bytes as a stream.

src/manta/utils.py

@@ -1,11 +1,13 @@
 from amaranth import *
-from amaranth.sim import Simulator
 from amaranth.lib import data
+from amaranth.lib import wiring
+from amaranth.lib.wiring import In, Out
+from amaranth.sim import Simulator
 from abc import ABC, abstractmethod
 import os
 
 
-class MantaCore(ABC, Elaboratable):
+class MantaCore(ABC, wiring.Component):
 
     @property
     @abstractmethod

test/test_io_core_hw.py

@@ -7,7 +7,7 @@ import pytest
 from random import randint
 
 
-class IOCoreLoopbackTest(Elaboratable):
+class IOCoreLoopbackTest(wiring.Component):
     def __init__(self, platform, port):
         self.platform = platform
         self.port = port

test/test_logic_analyzer_hw.py

@@ -6,7 +6,7 @@ from manta.utils import *
 import pytest
 
 
-class LogicAnalyzerCounterTest(Elaboratable):
+class LogicAnalyzerCounterTest(wiring.Component):
     def __init__(self, platform, port):
         self.platform = platform
         self.port = port

test/test_mem_core_hw.py

@@ -14,7 +14,7 @@ configuration, or a standard one.
 """
 
 
-class MemoryCoreLoopbackTest(Elaboratable):
+class MemoryCoreLoopbackTest(wiring.Component):
     def __init__(self, platform, width, depth, port):
         self.platform = platform
         self.width = width