update read responses to use D as preamble

src/manta/uart_iface/__init__.py

@@ -75,9 +75,9 @@ class UARTInterface:
         assert response is not None, "No reponse received."
 
         response_str = response.decode('ascii')
-        assert response_str[0] == 'M', "Bad message recieved, incorrect preamble."
-        assert response_str[-1] == '\n', "Bad message received, incorrect EOL."
+        assert response_str[0] == 'D', "Bad message recieved, incorrect preamble."
         assert response_str[-2] == '\r', "Bad message received, incorrect EOL."
+        assert response_str[-1] == '\n', "Bad message received, incorrect EOL."
         assert len(response_str) == 7, f"Wrong number of bytes received, expecting 7 but got {len(response)}."
 
         return int(response_str[1:5], 16)
@@ -104,7 +104,7 @@ class UARTInterface:
         for i in range(0, len(addrs), self.chunk_size):
             addr_chunk = addrs[i:i+self.chunk_size]
 
-            outbound_bytes = [f"M{addr:04X}\r\n".encode('ascii') for addr in addr_chunk]
+            outbound_bytes = [f"R{addr:04X}\r\n".encode('ascii') for addr in addr_chunk]
             outbound_bytes = b"".join(outbound_bytes)
 
             self.ser.write(outbound_bytes)
@@ -155,7 +155,7 @@ class UARTInterface:
             data_chunk = datas[i:i+self.chunk_size]
 
 
-            outbound_bytes = [f"M{a:04X}{d:04X}\r\n" for a, d in zip(addr_chunk, data_chunk)]
+            outbound_bytes = [f"W{a:04X}{d:04X}\r\n" for a, d in zip(addr_chunk, data_chunk)]
             outbound_bytes = [ob.encode('ascii') for ob in outbound_bytes]
             outbound_bytes = b"".join(outbound_bytes)
 

src/manta/uart_iface/bridge_tx.v

@@ -15,10 +15,10 @@ module bridge_tx (
     function [7:0] to_ascii_hex;
         // convert a number from 0-15 into the corresponding ascii char
         input [3:0] n;
-        to_ascii_hex = (n > 10) ? (n + 8'h30) : (n + 8'h41 - 'd10);
+        to_ascii_hex = (n < 10) ? (n + 8'h30) : (n + 8'h41 - 'd10);
     endfunction
 
-    localparam PREAMBLE = 8'h4D;
+    localparam PREAMBLE = "D";
     localparam CR = 8'h0D;
     localparam LF = 8'h0A;
 

test/functional_sim/bridge_tx_tb.sv

@@ -22,7 +22,7 @@ bridge_tx btx (
     .clk(clk),
 
     .data_i(tb_btx_data),
-    .rw_i(1'b1),
+    .rw_i(1'b0),
     .valid_i(tb_btx_valid),
 
     .data_o(btx_utx_data),
@@ -33,7 +33,7 @@ reg [7:0] btx_utx_data;
 reg btx_utx_start;
 reg utx_btx_done;
 
-uart_tx #(.CLOCKS_PER_BAUD(/* CLOCKS_PER_BAUD */)) utx (
+uart_tx #(.CLOCKS_PER_BAUD(10)) utx (
     .clk(clk),
 
     .data_i(btx_utx_data),