refactored logic analyzer working in sim

src/manta/logic_analyzer/__init__.py

@@ -33,7 +33,7 @@ class LogicAnalyzerCore(Elaboratable):
         # Submodules
         self.fsm = LogicAnalyzerFSM(self.config, base_addr, interface)
         self.trig_blk = LogicAnalyzerTriggerBlock(
-            self.config, self.fsm.get_max_addr() + 1, interface
+            self.probes, self.fsm.get_max_addr() + 1, interface
         )
         self.sample_mem = LogicAnalyzerSampleMemory(
             self.config, self.trig_blk.get_max_addr() + 1, interface
@@ -182,6 +182,7 @@ class LogicAnalyzerCore(Elaboratable):
             self.valid_o.eq(sample_mem.valid_o),
             # Non-bus Connections
             fsm.trigger.eq(trig_blk.trig),
+            sample_mem.user_addr.eq(fsm.r.write_pointer),
             sample_mem.user_we.eq(fsm.write_enable),
         ]
 

src/manta/logic_analyzer/trigger_block.py

@@ -5,13 +5,9 @@ from ..io_core import IOCore
 class LogicAnalyzerTriggerBlock(Elaboratable):
     """ """
 
-    def __init__(self, config, base_addr, interface):
-        self.config = config
-
+    def __init__(self, probes, base_addr, interface):
         # Instantiate a bunch of trigger blocks
-        self.probes = [
-            Signal(width, name=name) for name, width in self.config["probes"].items()
-        ]
+        self.probes = probes
         self.triggers = [LogicAnalyzerTrigger(p) for p in self.probes]
 
         # Make IO core for everything

test/test_logic_analyzer_sim.py

@@ -33,19 +33,23 @@ def print_data_at_addr(addr):
 
 def set_fsm_register(name, data):
     addr = la.fsm.r.mmap[f"{name}_buf"]["addrs"][0]
+    strobe_addr = la.fsm.r.base_addr
 
-    yield from write_register(la, 0, 0)
+    yield from write_register(la, strobe_addr, 0)
     yield from write_register(la, addr, data)
-    yield from write_register(la, 0, 1)
-    yield from write_register(la, 0, 0)
+    yield from write_register(la, strobe_addr, 1)
+    yield from write_register(la, strobe_addr, 0)
+
 
 def set_trig_blk_register(name, data):
     addr = la.trig_blk.r.mmap[f"{name}_buf"]["addrs"][0]
+    strobe_addr = la.trig_blk.r.base_addr
 
-    yield from write_register(la, 0, 0)
+    yield from write_register(la, strobe_addr, 0)
     yield from write_register(la, addr, data)
-    yield from write_register(la, 0, 1)
-    yield from write_register(la, 0, 0)
+    yield from write_register(la, strobe_addr, 1)
+    yield from write_register(la, strobe_addr, 0)
+
 
 def set_probe(name, value):
     probe = None
@@ -53,16 +57,19 @@ def set_probe(name, value):
         if p.name == name:
             probe = p
 
-    yield p.eq(value)
+    yield probe.eq(value)
 
-def test_do_you_fucking_work():
+
+def test_single_shot_capture():
     def testbench():
         # # ok nice what happens if we try to run the core, which includes:
         yield from set_fsm_register("request_stop", 1)
         yield from set_fsm_register("request_stop", 0)
 
         # setting triggers
-        yield from set_trig_blk_register("curly_op", la.trig_blk.triggers[0].operations["EQ"])
+        yield from set_trig_blk_register(
+            "curly_op", la.trig_blk.triggers[0].operations["EQ"]
+        )
         yield from set_trig_blk_register("curly_arg", 4)
 
         # setting trigger mode