add immediate capture mode to logic analyzer
This commit is contained in:
Fischer Moseley
parent
07ae9cc2e8
commit
ee18e10ae1
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@ -247,61 +247,83 @@ class LogicAnalyzerCore(Elaboratable):
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Cat(attrs["triggered"] for attrs in self.probe_signals.values()).any()
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)
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def increment_mod_sample_depth(self, m, signal):
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# m.d.sync += signal.eq((signal + 1) % self.config["sample_depth"])
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with m.If(signal == self.config["sample_depth"] - 1):
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m.d.sync += signal.eq(0)
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with m.Else():
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m.d.sync += signal.eq(signal + 1)
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def run_state_machine(self, m):
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self.prev_request_start = Signal(1)
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self.prev_request_stop = Signal(1)
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prev_request_start = Signal(1)
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prev_request_stop = Signal(1)
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request_start = self.registers.request_start
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request_stop = self.registers.request_stop
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trigger_mode = self.registers.trigger_mode
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trigger_loc = self.registers.trigger_loc
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state = self.registers.state
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rp = self.registers.read_pointer
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wp = self.registers.write_pointer
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we = self.sample_mem.user_we
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m.d.comb += self.sample_mem.user_addr.eq(wp)
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# Rising edge detection for start/stop requests
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m.d.sync += self.prev_request_start.eq(self.registers.request_start)
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m.d.sync += self.prev_request_stop.eq(self.registers.request_stop)
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m.d.sync += prev_request_start.eq(request_start)
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m.d.sync += prev_request_stop.eq(request_stop)
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m.d.comb += self.sample_mem.user_addr.eq(self.registers.write_pointer)
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with m.If(state == self.states["IDLE"]):
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m.d.sync += wp.eq(0)
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m.d.sync += rp.eq(0)
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m.d.sync += we.eq(0)
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with m.If(self.registers.state == self.states["IDLE"]):
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m.d.sync += self.registers.write_pointer.eq(0)
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m.d.sync += self.registers.read_pointer.eq(0)
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m.d.sync += self.sample_mem.user_we.eq(0) # or something like this
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with m.If((self.registers.request_start) & (~self.prev_request_start)):
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m.d.sync += self.registers.state.eq(self.states["MOVE_TO_POSITION"])
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with m.Elif(self.registers.state == self.states["MOVE_TO_POSITION"]):
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m.d.sync += self.registers.write_pointer.eq(
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self.registers.write_pointer + 1
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)
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m.d.sync += self.sample_mem.user_we.eq(1)
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with m.If(self.registers.write_pointer == self.registers.trigger_loc):
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with m.If(self.trig):
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m.d.sync += self.registers.state.eq(self.states["CAPTURING"])
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with m.If((request_start) & (~prev_request_start)):
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m.d.sync += we.eq(1)
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with m.If(trigger_mode == self.trigger_modes["IMMEDIATE"]):
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m.d.sync += state.eq(self.states["CAPTURING"])
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with m.Else():
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m.d.sync += self.registers.state.eq(self.states["IN_POSITION"])
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with m.If(trigger_loc == 0):
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m.d.sync += state.eq(self.states["IN_POSITION"])
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with m.Elif(self.registers.state == self.states["IN_POSITION"]):
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m.d.sync += self.registers.write_pointer.eq(
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(self.registers.write_pointer + 1) % self.config["sample_depth"]
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)
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m.d.sync += self.registers.read_pointer.eq(
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(self.registers.read_pointer + 1) % self.config["sample_depth"]
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)
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m.d.sync += self.sample_mem.user_we.eq(1)
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with m.Else():
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m.d.sync += state.eq(self.states["MOVE_TO_POSITION"])
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m.d.sync += state.eq(self.states["MOVE_TO_POSITION"])
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with m.Elif(state == self.states["MOVE_TO_POSITION"]):
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m.d.sync += wp.eq(wp + 1)
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with m.If(wp == trigger_loc):
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with m.If(self.trig):
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m.d.sync += state.eq(self.states["CAPTURING"])
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with m.Else():
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m.d.sync += state.eq(self.states["IN_POSITION"])
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self.increment_mod_sample_depth(m, rp)
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with m.Elif(state == self.states["IN_POSITION"]):
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self.increment_mod_sample_depth(m, wp)
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with m.If(self.trig):
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m.d.sync += self.registers.state.eq(self.states["CAPTURING"])
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with m.Elif(self.registers.state == self.states["CAPTURING"]):
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with m.If(self.registers.write_pointer == self.registers.read_pointer):
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m.d.sync += self.sample_mem.user_we.eq(0)
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m.d.sync += self.registers.state.eq(self.states["CAPTURED"])
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m.d.sync += state.eq(self.states["CAPTURING"])
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with m.Else():
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m.d.sync += self.registers.write_pointer.eq(
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(self.registers.write_pointer + 1) % self.config["sample_depth"]
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)
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self.increment_mod_sample_depth(m, rp)
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with m.If((self.registers.request_stop) & (~self.prev_request_stop)):
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m.d.sync += self.registers.state.eq(self.states["IDLE"])
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with m.Elif(state == self.states["CAPTURING"]):
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with m.If(wp == rp):
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m.d.sync += we.eq(0)
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m.d.sync += state.eq(self.states["CAPTURED"])
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with m.Else():
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self.increment_mod_sample_depth(m, wp)
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with m.If((request_stop) & (~prev_request_stop)):
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m.d.sync += state.eq(self.states["IDLE"])
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def elaborate(self, platform):
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m = Module()
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@ -6,70 +6,12 @@ from random import sample
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config = {
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"type": "logic_analyzer",
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"sample_depth": 1024,
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"trigger_loc": 500,
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"trigger_loc": 512,
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"probes": {"larry": 1, "curly": 3, "moe": 9},
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"triggers": ["moe RISING"],
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}
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# class SimulatedBusInterface():
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# def __init__(self, core):
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# self.core = core
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# def write(self, addrs, datas):
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# # Handle a single integer address and data
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# if isinstance(addrs, int) and isinstance(datas, int):
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# return self.write([addrs], [datas])
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# # Make sure address and datas are all integers
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# if not isinstance(addrs, list) or not isinstance(datas, list):
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# raise ValueError(
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# "Write addresses and data must be an integer or list of integers."
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# )
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# if not all(isinstance(a, int) for a in addrs):
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# raise ValueError("Write addresses must be all be integers.")
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# if not all(isinstance(d, int) for d in datas):
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# raise ValueError("Write data must all be integers.")
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# # I'm not sure if it's necessary to split outputs into chunks
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# # I think the output buffer doesn't really drop stuff, just the input buffer
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# for addr, data in zip(addrs, datas):
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# yield from write_register(self.core, addr, data)
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# def read(self, addrs):
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# # Handle a single integer address
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# if isinstance(addrs, int):
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# return self.read([addrs])[0]
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# # Make sure all list elements are integers
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# if not all(isinstance(a, int) for a in addrs):
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# raise ValueError("Read address must be an integer or list of integers.")
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# datas = []
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# for addr in addrs:
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# yield la.addr_i.eq(addr)
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# yield la.data_i.eq(0)
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# yield la.rw_i.eq(0)
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# yield la.valid_i.eq(1)
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# yield
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# yield la.addr_i.eq(0)
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# yield la.valid_i.eq(0)
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# # wait for output to be valid
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# while not (yield la.valid_o):
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# yield
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# datas.append( (yield la.data_o) )
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# return datas
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la = LogicAnalyzerCore(config, base_addr=0, interface=None)
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# interface = SimulatedBusInterface(la)
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# la.registers.interface = interface # unironically the least cursed part of this
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# la.sample_mem.interface = interface # unironically the least cursed part of this
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def print_data_at_addr(addr):
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# place read transaction on the bus
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@ -113,7 +55,7 @@ def test_do_you_fucking_work():
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) # right now this is not actually respected...oops
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# setting trigger location
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yield from set_logic_analyzer_register("trigger_loc", 500)
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yield from set_logic_analyzer_register("trigger_loc", 511)
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# starting capture
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yield from set_logic_analyzer_register("request_start", 1)
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