add working io_core autogeneration
This commit is contained in:
Fischer Moseley
parent
49021411ea
commit
060583d8fc
2
Makefile
2
Makefile
|
|
@ -31,7 +31,7 @@ auto_gen:
|
|||
python3 test/auto_gen/run_tests.py
|
||||
|
||||
# Build Examples
|
||||
NEXYS_A7_EXAMPLES := io_core_ether io_core_uart ps2_logic_analyzer video_sprite_ether video_sprite_uart block_mem_uart logic_analyzer_uart
|
||||
NEXYS_A7_EXAMPLES := io_core_ether io_core_uart ps2_logic_analyzer video_sprite_ether video_sprite_uart block_mem_uart logic_analyzer_uart large_io_core_uart
|
||||
|
||||
.PHONY: nexys_a7 $(NEXYS_A7_EXAMPLES)
|
||||
nexys_a7: $(NEXYS_A7_EXAMPLES)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,23 @@
|
|||
---
|
||||
cores:
|
||||
io_core:
|
||||
type: io
|
||||
|
||||
inputs:
|
||||
probe0: 1
|
||||
probe1: 2
|
||||
probe2: 8
|
||||
probe3: 20
|
||||
|
||||
outputs:
|
||||
probe4:
|
||||
width: 1
|
||||
initial_value: 1
|
||||
probe5: 2
|
||||
probe6: 8
|
||||
probe7: 20
|
||||
|
||||
uart:
|
||||
port: "auto"
|
||||
baudrate: 3000000
|
||||
clock_freq: 100000000
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
`default_nettype none
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module top_level (
|
||||
input wire clk,
|
||||
|
||||
input wire uart_txd_in,
|
||||
output logic uart_rxd_out,
|
||||
|
||||
input wire btnu,
|
||||
input wire btnd,
|
||||
input wire btnl,
|
||||
input wire btnr,
|
||||
input wire btnc,
|
||||
|
||||
input wire [15:0] sw,
|
||||
|
||||
output logic [15:0] led,
|
||||
output logic led16_b,
|
||||
output logic led16_g,
|
||||
output logic led16_r,
|
||||
output logic led17_b,
|
||||
output logic led17_g,
|
||||
output logic led17_r);
|
||||
|
||||
manta manta_inst (
|
||||
.clk(clk),
|
||||
|
||||
.rx(uart_txd_in),
|
||||
.tx(uart_rxd_out),
|
||||
|
||||
.btnu(btnu),
|
||||
.btnd(btnd),
|
||||
.btnl(btnl),
|
||||
.btnr(btnr),
|
||||
.btnc(btnc),
|
||||
.sw(sw),
|
||||
.led(led),
|
||||
.led16_b(led16_b),
|
||||
.led16_g(led16_g),
|
||||
.led16_r(led16_r),
|
||||
.led17_b(led17_b),
|
||||
.led17_g(led17_g),
|
||||
.led17_r(led17_r));
|
||||
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
|
|
@ -0,0 +1,254 @@
|
|||
## This file is a general .xdc for the Nexys4 DDR Rev. C
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## This file has been modified from the default .xdc provided by Digilent for the Nexys A7
|
||||
|
||||
## Clock signal - uncomment _both_ of these lines to create clk_100mhz
|
||||
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk
|
||||
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk}];
|
||||
|
||||
##Switches
|
||||
|
||||
set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
|
||||
set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
|
||||
set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
|
||||
set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]
|
||||
set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]
|
||||
set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5]
|
||||
set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]
|
||||
set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7]
|
||||
set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8]
|
||||
set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9]
|
||||
set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10]
|
||||
set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11]
|
||||
set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12]
|
||||
set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13]
|
||||
set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14]
|
||||
set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15]
|
||||
|
||||
|
||||
## LEDs
|
||||
|
||||
set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0]
|
||||
set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1]
|
||||
set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2]
|
||||
set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3]
|
||||
set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4]
|
||||
set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5]
|
||||
set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6]
|
||||
set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7]
|
||||
set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8]
|
||||
set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9]
|
||||
set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10]
|
||||
set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11]
|
||||
set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12]
|
||||
set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13]
|
||||
set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14]
|
||||
set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15]
|
||||
|
||||
set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { led16_b }]; #IO_L5P_T0_D06_14 Sch=led16_b
|
||||
set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { led16_g }]; #IO_L10P_T1_D14_14 Sch=led16_g
|
||||
set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led16_r }]; #IO_L11P_T1_SRCC_14 Sch=led16_r
|
||||
set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led17_b }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b
|
||||
set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { led17_g }]; #IO_0_14 Sch=led17_g
|
||||
set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led17_r }]; #IO_L11N_T1_SRCC_14 Sch=led17_r
|
||||
|
||||
|
||||
##7 segment display
|
||||
|
||||
#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca
|
||||
#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb
|
||||
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc
|
||||
#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd
|
||||
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce
|
||||
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf
|
||||
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg
|
||||
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp
|
||||
|
||||
#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
|
||||
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
|
||||
#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
|
||||
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
|
||||
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
|
||||
#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6]
|
||||
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
|
||||
|
||||
|
||||
##Buttons
|
||||
|
||||
#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn
|
||||
|
||||
set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btnc }]; #IO_L9P_T1_DQS_14 Sch=btnc
|
||||
set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { btnu }]; #IO_L4N_T0_D05_14 Sch=btnu
|
||||
set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { btnl }]; #IO_L12P_T1_MRCC_14 Sch=btnl
|
||||
set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { btnr }]; #IO_L10N_T1_D15_14 Sch=btnr
|
||||
set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btnd }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd
|
||||
|
||||
|
||||
##Pmod Headers
|
||||
|
||||
|
||||
##Pmod Header JA
|
||||
|
||||
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L20N_T3_A19_15 Sch=ja[1]
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2]
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L21P_T3_DQS_15 Sch=ja[3]
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L18N_T2_A23_15 Sch=ja[4]
|
||||
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L16N_T2_A27_15 Sch=ja[7]
|
||||
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L16P_T2_A28_15 Sch=ja[8]
|
||||
#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L22N_T3_A16_15 Sch=ja[9]
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L22P_T3_A17_15 Sch=ja[10]
|
||||
|
||||
|
||||
##Pmod Header JB
|
||||
|
||||
#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1]
|
||||
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2]
|
||||
#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3]
|
||||
#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L15P_T2_DQS_15 Sch=jb[4]
|
||||
#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7]
|
||||
#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8]
|
||||
#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_0_15 Sch=jb[9]
|
||||
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10]
|
||||
|
||||
|
||||
##Pmod Header JC
|
||||
|
||||
#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L23N_T3_35 Sch=jc[1]
|
||||
#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L19N_T3_VREF_35 Sch=jc[2]
|
||||
#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L22N_T3_35 Sch=jc[3]
|
||||
#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L19P_T3_35 Sch=jc[4]
|
||||
#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L6P_T0_35 Sch=jc[7]
|
||||
#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22P_T3_35 Sch=jc[8]
|
||||
#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L21P_T3_DQS_35 Sch=jc[9]
|
||||
#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10]
|
||||
|
||||
|
||||
##Pmod Header JD
|
||||
|
||||
#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L21N_T3_DQS_35 Sch=jd[1]
|
||||
#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L17P_T2_35 Sch=jd[2]
|
||||
#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L17N_T2_35 Sch=jd[3]
|
||||
#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L20N_T3_35 Sch=jd[4]
|
||||
#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L15P_T2_DQS_35 Sch=jd[7]
|
||||
#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L20P_T3_35 Sch=jd[8]
|
||||
#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15N_T2_DQS_35 Sch=jd[9]
|
||||
#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10]
|
||||
|
||||
|
||||
##Pmod Header JXADC
|
||||
|
||||
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVDS } [get_ports { xa_n[0] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1]
|
||||
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVDS } [get_ports { xa_p[0] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1]
|
||||
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVDS } [get_ports { xa_n[1] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2]
|
||||
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVDS } [get_ports { xa_p[1] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2]
|
||||
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVDS } [get_ports { xa_n[2] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3]
|
||||
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVDS } [get_ports { xa_p[2] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3]
|
||||
#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVDS } [get_ports { xa_n[3] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4]
|
||||
#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVDS } [get_ports { xa_p[3] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4]
|
||||
|
||||
|
||||
##VGA Connector
|
||||
|
||||
#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0]
|
||||
#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1]
|
||||
#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2]
|
||||
#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3]
|
||||
#
|
||||
#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0]
|
||||
#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1]
|
||||
#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2]
|
||||
#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3]
|
||||
#
|
||||
#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0]
|
||||
#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L4N_T0_35 Sch=vga_b[1]
|
||||
#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2]
|
||||
#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L4P_T0_35 Sch=vga_b[3]
|
||||
|
||||
#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { vga_hs }]; #IO_L4P_T0_15 Sch=vga_hs
|
||||
#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vga_vs }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs
|
||||
|
||||
##Micro SD Connector
|
||||
|
||||
#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset
|
||||
#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd
|
||||
#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { sd_sck }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck
|
||||
#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L16N_T2_35 Sch=sd_cmd
|
||||
#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0]
|
||||
#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1]
|
||||
#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2]
|
||||
#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3]
|
||||
|
||||
|
||||
##Accelerometer
|
||||
|
||||
#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { acl_miso }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso
|
||||
#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { acl_mosi }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi
|
||||
#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { acl_sclk }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk
|
||||
#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { acl_csn }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn
|
||||
#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { acl_int[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1]
|
||||
#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { acl_int[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2]
|
||||
|
||||
|
||||
##Temperature Sensor
|
||||
|
||||
#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { tmp_scl }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl
|
||||
#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { tmp_sda }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda
|
||||
#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { tmp_int }]; #IO_L6N_T0_VREF_15 Sch=tmp_int
|
||||
#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { tmp_ct }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct
|
||||
|
||||
##Omnidirectional Microphone
|
||||
|
||||
#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { m_clk }]; #IO_25_35 Sch=m_clk
|
||||
#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { m_data }]; #IO_L24N_T3_35 Sch=m_data
|
||||
#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { m_lrsel }]; #IO_0_35 Sch=m_lrsel
|
||||
|
||||
|
||||
##PWM Audio Amplifier
|
||||
|
||||
#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { aud_pwm }]; #IO_L4N_T0_15 Sch=aud_pwm
|
||||
#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { aud_sd }]; #IO_L6P_T0_15 Sch=aud_sd
|
||||
|
||||
|
||||
##USB-RS232 Interface
|
||||
|
||||
set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in
|
||||
set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out
|
||||
#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { uart_cts }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts
|
||||
#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { uart_rts }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts
|
||||
|
||||
##USB HID (PS/2)
|
||||
|
||||
#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { ps2_clk }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk
|
||||
#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { ps2_data }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data
|
||||
|
||||
|
||||
##SMSC Ethernet PHY
|
||||
|
||||
#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc
|
||||
#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio
|
||||
#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn
|
||||
#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { eth_crsdv }]; #IO_L6N_T0_VREF_16 Sch=eth_crs/udv
|
||||
#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr
|
||||
#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0]
|
||||
#set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1]
|
||||
#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { eth_txen }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen
|
||||
#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0]
|
||||
#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1]
|
||||
#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { eth_refclk }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk
|
||||
#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { eth_intn }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn
|
||||
|
||||
|
||||
##Quad SPI Flash
|
||||
|
||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
|
||||
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
|
||||
#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_csn }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn
|
||||
|
||||
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
# Internal Dependencies
|
||||
from .hdl_utils import *
|
||||
from .utils import *
|
||||
from .la_core import *
|
||||
from .io_core import *
|
||||
from .block_mem_core import *
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
from ..hdl_utils import *
|
||||
from ..utils import *
|
||||
|
||||
from math import ceil, log2
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
from ..hdl_utils import *
|
||||
from ..utils import *
|
||||
|
||||
# Lazy and selective imports for quick builds!
|
||||
from scapy.interfaces import get_if_list
|
||||
|
|
|
|||
|
|
@ -1,85 +1,112 @@
|
|||
from ..hdl_utils import *
|
||||
from ..utils import *
|
||||
from math import ceil
|
||||
|
||||
class Probe:
|
||||
def __init__(self, name, width, base_addr, interface):
|
||||
assert isinstance(width, int), f"Probe {name} must have integer width."
|
||||
assert width > 0, f"Probe {name} must have positive width."
|
||||
|
||||
class IOCoreProbe:
|
||||
def __init__(self, name, width, direction, base_addr, interface):
|
||||
self.name = name
|
||||
self.width = width
|
||||
self.direction = direction
|
||||
self.base_addr = base_addr
|
||||
self.interface = interface
|
||||
|
||||
def set(self, data):
|
||||
# make sure that we're an output probe
|
||||
assert self.direction == "output", "Cannot set value of input port."
|
||||
n_addrs = ceil(self.width / 16)
|
||||
self.addrs = list(range(base_addr, base_addr + n_addrs))
|
||||
|
||||
# check that value is within range for the width of the probe
|
||||
assert isinstance(data, int), "Data must be an integer."
|
||||
if data > 0:
|
||||
assert data <= (2**self.width) - 1, f"Unsigned value too large for probe of width {self.width}"
|
||||
|
||||
elif data < 0:
|
||||
assert data >= -(2**(self.width-1))-1, f"Signed value too large for probe of width {self.width}"
|
||||
assert data <= (2**(self.width-1))-1, f"Signed value too large for probe of width {self.width}"
|
||||
|
||||
self.interface.write(self.base_addr, data)
|
||||
class InputProbe(Probe):
|
||||
def __init__(self, name, width, base_addr, interface):
|
||||
super().__init__(name, width, base_addr, interface)
|
||||
|
||||
def get(self):
|
||||
return self.interface.read(self.base_addr)
|
||||
return pack_16bit_words(self.interface.read(self.addrs))
|
||||
|
||||
class OutputProbe(Probe):
|
||||
def __init__(self, name, width, base_addr, initial_value, interface):
|
||||
super().__init__(name, width, base_addr, interface)
|
||||
self.initial_value = initial_value
|
||||
|
||||
def get(self):
|
||||
return pack_16bit_words(self.interface.read(self.addrs))
|
||||
|
||||
def set(self, value):
|
||||
# check that value is an integer
|
||||
assert isinstance(value, int), "Value must be an integer."
|
||||
|
||||
# check that value is within range for the width of the probe
|
||||
if value > 0:
|
||||
assert data <= (2**self.width) - 1, f"Unsigned value too large for probe of width {self.width}"
|
||||
|
||||
elif value < 0:
|
||||
assert abs(data) <= (2**(self.width-1))-1, f"Signed value too large for probe of width {self.width}"
|
||||
|
||||
data = unpack_16_bit_words(value)
|
||||
self.interface.write(self.addrs, data)
|
||||
|
||||
class IOCore:
|
||||
def __init__(self, config, name, base_addr, interface):
|
||||
self.name = name
|
||||
self.base_addr = base_addr
|
||||
self.interface = interface
|
||||
|
||||
# Warn if unrecognized options have been given
|
||||
for option in config:
|
||||
if option not in ["type", "inputs", "outputs"]:
|
||||
print(f"Warning: Ignoring unrecognized option '{option}' in IO core '{self.name}'")
|
||||
|
||||
# make sure we have ports defined
|
||||
assert ('inputs' in config) or ('outputs' in config), "No input or output ports specified."
|
||||
|
||||
# add input probes to core
|
||||
# check for unrecognized options
|
||||
for option in config:
|
||||
if option not in ["type", "inputs", "outputs", "user_clock"]:
|
||||
print(f"Warning: Ignoring unrecognized option '{option}' in IO core '{self.name}'")
|
||||
|
||||
# add user clock
|
||||
self.user_clock = False
|
||||
if "user_clock" in config:
|
||||
assert isinstance(config["user_clock"], bool), "Option user_clock must be a boolean."
|
||||
self.user_clock = config["user_clock"]
|
||||
|
||||
# add probes to core
|
||||
self.probes = []
|
||||
probe_base_addr = self.base_addr
|
||||
last_used_addr = self.base_addr # start at one since strobe register is at BASE_ADDR
|
||||
if 'inputs' in config:
|
||||
for name, width in config["inputs"].items():
|
||||
# make sure inputs are of reasonable width
|
||||
assert isinstance(width, int), f"Probe {name} must have integer width."
|
||||
assert width > 0, f"Probe {name} must have positive width."
|
||||
|
||||
probe = IOCoreProbe(name, width, "input", probe_base_addr, self.interface)
|
||||
|
||||
# add friendly name, so users can do Manta.my_io_core.my_probe.set() for example
|
||||
setattr(self, name, probe)
|
||||
probe = InputProbe(name, width, last_used_addr + 1, interface)
|
||||
self.probes.append(probe)
|
||||
|
||||
self.max_addr = probe_base_addr
|
||||
probe_base_addr += 1
|
||||
setattr(self, probe.name, probe) # add friendly name so users can do my_io_core.my_probe.set()
|
||||
last_used_addr = probe.addrs[-1]
|
||||
|
||||
# add output probes to core
|
||||
if 'outputs' in config:
|
||||
for name, width in config["outputs"].items():
|
||||
# make sure inputs are of reasonable width
|
||||
assert isinstance(width, int), f"Probe {name} must have integer width."
|
||||
assert width > 0, f"Probe {name} must have positive width."
|
||||
for name, params in config["outputs"].items():
|
||||
# get width and initial value from config
|
||||
if isinstance(params, int):
|
||||
width = params
|
||||
initial_value = 0
|
||||
|
||||
probe = IOCoreProbe(name, width, "output", probe_base_addr, self.interface)
|
||||
elif "width" in params and "initial_value" in params:
|
||||
width = params["width"]
|
||||
initial_value = params["initial_value"]
|
||||
|
||||
# add friendly name, so users can do Manta.my_io_core.my_probe.set() for example
|
||||
setattr(self, name, probe)
|
||||
else:
|
||||
raise ValueError(f"Unable to determine probe width and initial value for {probe}")
|
||||
|
||||
# add probe to core
|
||||
probe = OutputProbe(name, width, last_used_addr + 1, initial_value, interface)
|
||||
self.probes.append(probe)
|
||||
|
||||
self.max_addr = probe_base_addr
|
||||
probe_base_addr += 1
|
||||
setattr(self, probe.name, probe) # add friendly name so users can do my_io_core.my_probe.set()
|
||||
last_used_addr = self.probes[-1].addrs[-1]
|
||||
|
||||
self.max_addr = last_used_addr
|
||||
|
||||
def hdl_inst(self):
|
||||
inst = VerilogManipulator("io_core/io_core_inst_tmpl.v")
|
||||
inst.sub(self.name, "/* MODULE_NAME */")
|
||||
inst.sub(self.name + "_inst", "/* INST_NAME */")
|
||||
|
||||
# tie user_clock to bus_clk if external clock is not being used
|
||||
if not self.user_clock:
|
||||
inst.sub("clk", "/* USER_CLK */")
|
||||
|
||||
else:
|
||||
inst.sub(f"{self.name}_user_clk", "/* USER_CLK */")
|
||||
|
||||
probes = {probe.name:probe.width for probe in self.probes}
|
||||
|
||||
inst_ports = inst.net_conn(probes, trailing_comma=True)
|
||||
|
|
@ -87,6 +114,82 @@ class IOCore:
|
|||
|
||||
return inst.get_hdl()
|
||||
|
||||
def gen_memory_handling(self):
|
||||
rcsb = "" # read case statement body
|
||||
wcsb = "" # write case statement body
|
||||
for probe in self.probes:
|
||||
if probe.width <= 16:
|
||||
rcsb += f"BASE_ADDR + {probe.addrs[0]}: data_o <= {probe.name}_buf;\n"
|
||||
|
||||
if isinstance(probe, OutputProbe):
|
||||
wcsb += f"BASE_ADDR + {probe.addrs[0]}: {probe.name}_buf <= data_i;\n"
|
||||
|
||||
else:
|
||||
for i in range(ceil(probe.width/16)):
|
||||
top = ((i + 1) * 16) - 1
|
||||
btm = i * 16
|
||||
if top > probe.width - 1:
|
||||
top = probe.width - 1
|
||||
|
||||
rcsb += f"BASE_ADDR + {probe.addrs[i]}: data_o <= {probe.name}_buf[{top}:{btm}];\n"
|
||||
|
||||
if isinstance(probe, OutputProbe):
|
||||
wcsb += f"BASE_ADDR + {probe.addrs[i]}: {probe.name}_buf[{top}:{btm}] <= data_i;\n"
|
||||
|
||||
# remove trailing newline
|
||||
return rcsb.rstrip(), wcsb.rstrip()
|
||||
|
||||
def gen_input_probe_bufs(self):
|
||||
ipb = []
|
||||
for probe in self.probes:
|
||||
if isinstance(probe, InputProbe):
|
||||
if probe.width == 1:
|
||||
ipb.append(f"reg {probe.name}_buf = 0;")
|
||||
|
||||
else:
|
||||
ipb.append(f"reg [{probe.width-1}:0] {probe.name}_buf = 0;")
|
||||
|
||||
return '\n'.join(ipb)
|
||||
|
||||
|
||||
|
||||
def gen_output_probe_bufs(self):
|
||||
opb = []
|
||||
for probe in self.probes:
|
||||
if isinstance(probe, OutputProbe):
|
||||
if probe.width == 1:
|
||||
opb.append(f"reg {probe.name}_buf = {probe.initial_value};")
|
||||
|
||||
else:
|
||||
opb.append(f"reg [{probe.width-1}:0] {probe.name}_buf = {probe.initial_value};")
|
||||
|
||||
return '\n'.join(opb)
|
||||
|
||||
|
||||
def gen_output_probe_initial_values(self):
|
||||
opiv = []
|
||||
for probe in self.probes:
|
||||
if isinstance(probe, OutputProbe):
|
||||
opiv.append(f"{probe.name} = {probe.initial_value};")
|
||||
|
||||
return '\n'.join(opiv)
|
||||
|
||||
|
||||
def gen_update_input_buffers(self):
|
||||
uib = []
|
||||
for probe in self.probes:
|
||||
if isinstance(probe, InputProbe):
|
||||
uib.append(f"{probe.name}_buf <= {probe.name};")
|
||||
|
||||
return '\n'.join(uib)
|
||||
|
||||
def gen_update_output_buffers(self):
|
||||
uob = []
|
||||
for probe in self.probes:
|
||||
if isinstance(probe, OutputProbe):
|
||||
uob.append(f"{probe.name} <= {probe.name}_buf;")
|
||||
|
||||
return '\n'.join(uob)
|
||||
|
||||
def hdl_def(self):
|
||||
io_core = VerilogManipulator("io_core/io_core_def_tmpl.v")
|
||||
|
|
@ -99,44 +202,27 @@ class IOCore:
|
|||
io_core.sub(top_level_ports, "/* TOP_LEVEL_PORTS */")
|
||||
|
||||
# generate memory handling
|
||||
rcsb = "" # read case statement body
|
||||
wcsb = "" # write case statement body
|
||||
for probe in self.probes:
|
||||
|
||||
# add to read block
|
||||
if probe.width == 16:
|
||||
rcsb += f"{probe.base_addr}: data_o <= {probe.name};\n"
|
||||
|
||||
else:
|
||||
rcsb += f"{probe.base_addr}: data_o <= {{{16-probe.width}'b0, {probe.name}}};\n"
|
||||
|
||||
|
||||
# if output, add to write block
|
||||
if probe.direction == "output":
|
||||
if probe.width == 1:
|
||||
wcsb += f"{probe.base_addr}: {probe.name} <= data_i[0];\n"
|
||||
|
||||
elif probe.width == 16:
|
||||
wcsb += f"{probe.base_addr}: {probe.name} <= data_i;\n"
|
||||
|
||||
else:
|
||||
wcsb += f"{probe.base_addr}: {probe.name} <= data_i[{probe.width-1}:0];\n"
|
||||
|
||||
# remove trailing newline
|
||||
rcsb = rcsb.rstrip()
|
||||
wcsb = wcsb.rstrip()
|
||||
|
||||
rcsb, wcsb = self.gen_memory_handling()
|
||||
io_core.sub(rcsb, "/* READ_CASE_STATEMENT_BODY */")
|
||||
io_core.sub(wcsb, "/* WRITE_CASE_STATEMENT_BODY */")
|
||||
|
||||
# generate input and output probe buffers
|
||||
io_core.sub(self.gen_input_probe_bufs(), "/* INPUT_PROBE_BUFFERS */")
|
||||
io_core.sub(self.gen_output_probe_bufs(), "/* OUTPUT_PROBE_BUFFERS */")
|
||||
io_core.sub(self.gen_output_probe_initial_values(), "/* OUTPUT_PROBE_INITIAL_VALUES */")
|
||||
io_core.sub(self.gen_update_input_buffers(), "/* UPDATE_INPUT_BUFFERS */")
|
||||
io_core.sub(self.gen_update_output_buffers(), "/* UPDATE_OUTPUT_BUFFERS */")
|
||||
|
||||
return io_core.get_hdl()
|
||||
|
||||
|
||||
|
||||
def hdl_top_level_ports(self):
|
||||
ports = []
|
||||
|
||||
if self.user_clock:
|
||||
ports.append(f"input wire {self.name}_user_clock")
|
||||
|
||||
for probe in self.probes:
|
||||
net_type = "input wire " if probe.direction == "input" else "output reg "
|
||||
net_type = "input wire " if isinstance(probe, InputProbe) else "output reg "
|
||||
name_def = probe.name if probe.width == 1 else f"[{probe.width-1}:0] {probe.name}"
|
||||
ports.append(net_type + name_def)
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
module /* MODULE_NAME */ (
|
||||
input wire clk,
|
||||
input wire bus_clk,
|
||||
input wire user_clk,
|
||||
|
||||
// ports
|
||||
/* TOP_LEVEL_PORTS */
|
||||
|
|
@ -19,7 +20,32 @@ module /* MODULE_NAME */ (
|
|||
|
||||
parameter BASE_ADDR = 0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
reg strobe = 0;
|
||||
|
||||
// input probe buffers
|
||||
/* INPUT_PROBE_BUFFERS */
|
||||
|
||||
// output probe buffers
|
||||
/* OUTPUT_PROBE_BUFFERS */
|
||||
|
||||
// output probe initial values
|
||||
initial begin
|
||||
/* OUTPUT_PROBE_INITIAL_VALUES */
|
||||
end
|
||||
|
||||
// synchronize buffers and probes on strobe
|
||||
always @(posedge user_clk) begin
|
||||
if(strobe) begin
|
||||
// update input buffers from input probes
|
||||
/* UPDATE_INPUT_BUFFERS */
|
||||
|
||||
// update output buffers from output probes
|
||||
/* UPDATE_OUTPUT_BUFFERS */
|
||||
end
|
||||
end
|
||||
|
||||
// handle bus operations
|
||||
always @(posedge bus_clk) begin
|
||||
addr_o <= addr_i;
|
||||
data_o <= data_i;
|
||||
rw_o <= rw_i;
|
||||
|
|
@ -31,6 +57,8 @@ module /* MODULE_NAME */ (
|
|||
// reads
|
||||
if(!rw_i) begin
|
||||
case (addr_i)
|
||||
BASE_ADDR + 0: data_o <= strobe;
|
||||
|
||||
/* READ_CASE_STATEMENT_BODY */
|
||||
endcase
|
||||
end
|
||||
|
|
@ -38,6 +66,8 @@ module /* MODULE_NAME */ (
|
|||
// writes
|
||||
else begin
|
||||
case (addr_i)
|
||||
BASE_ADDR + 0: strobe <= data_i;
|
||||
|
||||
/* WRITE_CASE_STATEMENT_BODY */
|
||||
endcase
|
||||
end
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
/* MODULE_NAME */ /* INST_NAME */ (
|
||||
.clk(clk),
|
||||
.bus_clk(clk),
|
||||
.user_clk(/* USER_CLK */),
|
||||
|
||||
// ports
|
||||
/* INST_PORTS */
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
from ..hdl_utils import *
|
||||
from ..utils import *
|
||||
|
||||
from datetime import datetime
|
||||
from pkg_resources import get_distribution
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
from ..hdl_utils import *
|
||||
from ..utils import *
|
||||
|
||||
class UARTInterface:
|
||||
def __init__(self, config):
|
||||
|
|
|
|||
|
|
@ -1,5 +1,20 @@
|
|||
import pkgutil
|
||||
|
||||
def pack_16bit_words(data):
|
||||
"""Takes a list of integers, interprets them as 16-bit integers, and
|
||||
concatenates them together in little-endian order."""
|
||||
for d in data:
|
||||
if d > 0:
|
||||
assert d < 2**16-1, "Unsigned integer too large."
|
||||
|
||||
if d < 0:
|
||||
assert d < 2**15-1, "Signed integer too large."
|
||||
|
||||
return int(''.join([f'{i:016b}' for i in data[::-1]]), 2)
|
||||
|
||||
def unpack_16bit_words(data):
|
||||
pass
|
||||
|
||||
class VerilogManipulator:
|
||||
def __init__(self, filepath=None):
|
||||
if filepath is not None:
|
||||
|
|
@ -1,15 +1,24 @@
|
|||
---
|
||||
io_core:
|
||||
type: io
|
||||
cores:
|
||||
io_core:
|
||||
type: io
|
||||
user_clock: True
|
||||
|
||||
inputs:
|
||||
probe0: 1
|
||||
probe1: 2
|
||||
probe2: 8
|
||||
probe3: 20
|
||||
inputs:
|
||||
probe0: 1
|
||||
probe1: 2
|
||||
probe2: 8
|
||||
probe3: 20
|
||||
|
||||
outputs:
|
||||
probe4: 1
|
||||
probe5: 2
|
||||
probe6: 8
|
||||
probe7: 20
|
||||
outputs:
|
||||
probe4:
|
||||
width: 1
|
||||
initial_value: 1
|
||||
probe5: 2
|
||||
probe6: 8
|
||||
probe7: 20
|
||||
|
||||
uart:
|
||||
port: "auto"
|
||||
baudrate: 3000000
|
||||
clock_freq: 100000000
|
||||
|
|
|
|||
Loading…
Reference in New Issue