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10593c768e · logic_analyzer: fix #35, patch typos in trigger set logic · Updated 2025-04-08 19:18:44 +02:00

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62049bac84 · meta: replace Signal(1) with Signal() · Updated 2026-01-20 00:31:12 +01:00

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ba7e5932c1 · Deployed 10593c7 to dev with MkDocs 1.6.1 and mike 2.1.3 · Updated 2025-04-08 19:19:15 +02:00

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75d9a82979 · logic_analyzer: fix #35, patch typos in trigger set logic · Updated 2025-04-08 09:12:57 +02:00

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81ca4908b0 · meta: add pytest-xdist to pyproject.toml · Updated 2025-04-07 18:07:13 +02:00

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277d561a63 · logic_analyzer: fix missing import · Updated 2024-10-08 16:37:31 +02:00

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416d537cec · uart: begin bringing up COBS · Updated 2024-10-06 17:20:27 +02:00

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562734cb84 · examples: add nexys video uart_io_core and uart_host_to_fpga_mem · Updated 2024-05-19 23:48:59 +02:00    luke

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b85e4bc777 · mem: quick hack to add user_clock · Updated 2024-05-19 23:07:40 +02:00    luke

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f4c24976c6 · web: implement synchronous IO with web and service workers · Updated 2024-04-18 20:21:51 +02:00    luke

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