update template naming for consistency

2023-07-31 06:54:32 -07:00 · 2023-07-31 06:54:32 -07:00 · 4abc2e2cae
parent c37a6e5e90
commit 4abc2e2cae
4 changed files with 2 additions and 12 deletions
--- a/src/manta/uart_iface/init.py
+++ b/src/manta/uart_iface/init.py
@ -176,11 +176,11 @@ class UARTInterface:
        return bridge_tx_def + '\n' + uart_tx_def

    def rx_hdl_inst(self):
-        rx = VerilogManipulator("uart_iface/uart_rx_bridge_rx_inst_templ.v")
+        rx = VerilogManipulator("uart_iface/uart_rx_bridge_rx_inst_tmpl.v")
        rx.sub(self.clocks_per_baud, "/* CLOCKS_PER_BAUD */")
        return rx.get_hdl()

    def tx_hdl_inst(self):
-        tx = VerilogManipulator("uart_iface/uart_tx_bridge_tx_inst_templ.v")
+        tx = VerilogManipulator("uart_iface/uart_tx_bridge_tx_inst_tmpl.v")
        tx.sub(self.clocks_per_baud, "/* CLOCKS_PER_BAUD */")
        return tx.get_hdl()
--- a/src/manta/uart_iface/uart_rx_bridge_rx_inst_templ.v
+++ b/src/manta/uart_iface/uart_rx_bridge_rx_inst_templ.v
--- a/src/manta/uart_iface/uart_tx_bridge_tx_inst_templ.v
+++ b/src/manta/uart_iface/uart_tx_bridge_tx_inst_templ.v
--- a/test/auto_gen/valid_configs/2_lut_ram.yaml
+++ b/test/auto_gen/valid_configs/2_lut_ram.yaml
@ -1,10 +0,0 @@
---
-cores:
-  my_lut_mem:
-    type: lut_mem
-    size: 64
-
-uart:
-  port: "auto"
-  baudrate: 115200
-  clock_freq: 100000000