track amaranth release, not main repo

pyproject.toml

@@ -7,7 +7,7 @@ authors = [
 description = "An In-Situ Debugging Tool for Programmable Hardware"
 readme = "README.md"
 dependencies = [
-  "amaranth[builtin-yosys]@git+https://github.com/amaranth-lang/amaranth",
+  "amaranth[builtin-yosys]",
   "PyYAML",
   "pyserial",
   "pyvcd",

src/manta/utils.py

@@ -109,21 +109,36 @@ def write_register(module, addr, data):
 
 def xilinx_tools_installed():
     """
-    Return whether Vivado is installed, by checking if the VIVADO environment variable is set.
+    Return whether Vivado is installed, by checking if the VIVADO environment variable is set,
+    or if the binary exists on PATH.
 
     This variable should point to the binary itself, not just the folder it's located in
     (ie, /tools/Xilinx/Vivado/2023.1/bin/vivado, not /tools/Xilinx/Vivado/2023.1/bin)
     """
-    return "VIVADO" in os.environ
+    from shutil import which
+    return ("VIVADO" in os.environ) or (which("vivado") is not None)
 
 
 def ice40_tools_installed():
     """
     Return whether the ice40 tools are installed, by checking if the YOSYS, NEXTPNR_ICE40,
-    ICEPACK, and ICEPROG environment variables are defined.
+    ICEPACK, and ICEPROG environment variables are defined, or if the binaries exist on PATH.
 
     # These variables should point to the binaries themselves, not just the folder it's located in
     # (ie, /tools/oss-cad-suite/bin/yosys, not /tools/oss-cad-suite/bin/)
     """
-    tools = ["YOSYS", "NEXTPNR_ICE40", "ICEPACK", "ICEPROG"]
-    return all(tool in os.environ for tool in tools)
+
+    # Check environment variables
+    env_vars = ["YOSYS", "NEXTPNR_ICE40", "ICEPACK", "ICEPROG"]
+    if all(var in os.environ for var in env_vars):
+        return True
+
+    # Check PATH
+    binaries = ["yosys", "nextpnr-ice40", "icepack", "iceprog"]
+    from shutil import which
+    if all([which(b) for b in binaries]):
+        return True
+
+    return False
+
+

test/test_logic_analyzer_hw.py

@@ -37,9 +37,9 @@ class LogicAnalyzerCounterTest(Elaboratable):
         m.submodules["manta"] = self.m
         uart_pins = platform.request("uart")
 
-        larry = self.m.la.probe_signals["larry"]["top_level"]
-        curly = self.m.la.probe_signals["curly"]["top_level"]
-        moe = self.m.la.probe_signals["moe"]["top_level"]
+        larry = self.m.la.probes[0]
+        curly = self.m.la.probes[1]
+        moe = self.m.la.probes[2]
 
         m.d.sync += larry.eq(larry + 1)
         m.d.sync += curly.eq(curly + 1)
@@ -75,10 +75,10 @@ class LogicAnalyzerCounterTest(Elaboratable):
 
 
 @pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed")
-def test_mem_core_xilinx():
+def test_logic_analyzer_core_xilinx():
     LogicAnalyzerCounterTest(Nexys4DDRPlatform(), "/dev/ttyUSB2").verify()
 
 
 @pytest.mark.skipif(not ice40_tools_installed(), reason="no toolchain installed")
-def test_mem_core_ice40():
+def test_logic_analyzer_core_ice40():
     LogicAnalyzerCounterTest(ICEStickPlatform(), "/dev/ttyUSB1").verify()