update submodule usage, tidy logic analyzer config check
This commit is contained in:
Fischer Moseley
parent
970499d137
commit
1528f569ef
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@ -54,9 +54,11 @@ Usage:
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def help():
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print(usage)
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def version():
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print(logo)
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def wrong_args():
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print('Wrong number of arguments, run "manta help" for usage.')
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@ -68,98 +68,102 @@ class LogicAnalyzerCore(Elaboratable):
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warn(f"Ignoring unrecognized option '{option}' in Logic Analyzer.")
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# Check sample depth is provided and positive
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if "sample_depth" not in config:
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sample_depth = config.get("sample_depth")
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if not sample_depth:
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raise ValueError("Logic Analyzer must have sample_depth specified.")
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if not isinstance(config["sample_depth"], int):
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raise ValueError("Logic Analyzer sample_depth must be an integer.")
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if config["sample_depth"] <= 0:
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raise ValueError("Logic Analyzer sample_depth must be positive.")
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if not isinstance(sample_depth, int) or sample_depth <= 0:
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raise ValueError("Logic Analyzer sample_depth must be a positive integer.")
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# Check probes
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if "probes" not in config:
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raise ValueError("Logic Analyzer must have at least one probe specified.")
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if len(config["probes"]) == 0:
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if "probes" not in config or len(config["probes"]) == 0:
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raise ValueError("Logic Analyzer must have at least one probe specified.")
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for name, width in config["probes"].items():
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if width < 0:
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raise ValueError(f"Width of probe {name} must be positive.")
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# Check triggers
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if "triggers" not in config:
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raise ValueError("Logic Analyzer must have at least one trigger specified.")
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if len(config["triggers"]) == 0:
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raise ValueError("Logic Analyzer must have at least one trigger specified.")
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# Check trigger location
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if "trigger_location" in config:
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if not isinstance(config["trigger_location"], int):
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raise ValueError("Trigger location must be an integer.")
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if config["trigger_location"] < 0:
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raise ValueError("Trigger location must be positive.")
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if config["trigger_location"] > config["sample_depth"]:
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raise ValueError("Trigger location cannot exceed sample depth.")
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# Check trigger mode, if provided
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if "trigger_mode" in config:
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valid_modes = ["single_shot", "incremental", "immediate"]
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if config["trigger_mode"] not in valid_modes:
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trigger_mode = config.get("trigger_mode")
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valid_modes = ["single_shot", "incremental", "immediate"]
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if trigger_mode and trigger_mode not in valid_modes:
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raise ValueError(
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f"Unrecognized trigger mode {config['trigger_mode']} provided."
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)
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# Check triggers
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if (trigger_mode) and (trigger_mode != "immediate"):
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if ("triggers" not in config) or (config["triggers"] == 0):
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raise ValueError(
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f"Unrecognized trigger mode {config['trigger_mode']} provided."
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"Logic Analyzer must have at least one trigger specified."
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)
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if config["trigger_mode"] == "incremental":
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if "trigger_location" in config:
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warn(
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"Ignoring option 'trigger_location', as 'trigger_mode' is set to immediate, and there is no trigger condition to wait for."
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)
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# Check trigger location
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trigger_location = config.get("trigger_location")
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if trigger_location:
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if not isinstance(trigger_location, int) or trigger_location < 0:
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raise ValueError("Trigger location must be a positive integer.")
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if trigger_location > config["sample_depth"]:
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raise ValueError("Trigger location cannot exceed sample depth.")
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if trigger_mode == "immediate":
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warn(
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"Ignoring option 'trigger_location', as 'trigger_mode' is set to immediate, and there is no trigger condition to wait for."
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)
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# Check triggers themselves
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for trigger in config["triggers"]:
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if not isinstance(trigger, str):
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raise ValueError("Trigger must be specified with a string.")
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if trigger_mode == "immediate":
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if "triggers" in config:
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warn(
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"Ignoring triggers as 'trigger_mode' is set to immediate, and there are no triggers to specify."
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)
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# Trigger conditions may be composed of either two or three components,
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# depending on the operation specified. In the case of operations that
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# don't need an argument (like DISABLE, RISING, FALLING, CHANGING) or
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# three statements in
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else:
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if ("triggers" not in config) or (len(config["triggers"]) == 0):
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raise ValueError("At least one trigger must be specified.")
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# Check the trigger operations
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components = trigger.strip().split(" ")
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if len(components) == 2:
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name, op = components
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if op not in ["DISABLE", "RISING", "FALLING", "CHANGING"]:
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for trigger in config.get("triggers"):
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if not isinstance(trigger, str):
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raise ValueError("Trigger must be specified with a string.")
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# Trigger conditions may be composed of either two or three components,
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# depending on the operation specified. In the case of operations that
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# don't need an argument (like DISABLE, RISING, FALLING, CHANGING) or
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# three statements in
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# Check the trigger operations
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components = trigger.strip().split(" ")
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if len(components) == 2:
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name, op = components
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if op not in ["DISABLE", "RISING", "FALLING", "CHANGING"]:
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raise ValueError(
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f"Unable to interpret trigger condition '{trigger}'."
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)
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elif len(components) == 3:
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name, op, arg = components
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if op not in ["GT", "LT", "GEQ", "LEQ", "EQ", "NEQ"]:
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raise ValueError(
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f"Unable to interpret trigger condition '{trigger}'."
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)
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else:
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raise ValueError(
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f"Unable to interpret trigger condition '{trigger}'."
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)
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elif len(components) == 3:
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name, op, arg = components
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if op not in ["GT", "LT", "GEQ", "LEQ", "EQ", "NEQ"]:
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raise ValueError(
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f"Unable to interpret trigger condition '{trigger}'."
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)
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else:
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raise ValueError(f"Unable to interpret trigger condition '{trigger}'.")
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# Check probe names
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if components[0] not in config["probes"]:
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raise ValueError(f"Unknown probe name '{components[0]}' specified.")
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# Check probe names
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if components[0] not in config["probes"]:
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raise ValueError(f"Unknown probe name '{components[0]}' specified.")
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def elaborate(self, platform):
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m = Module()
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# Add submodules
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m.submodules["fsm"] = fsm = self.fsm
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m.submodules["sample_mem"] = sample_mem = self.sample_mem
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m.submodules["trig_blk"] = trig_blk = self.trig_blk
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m.submodules.fsm = fsm = self.fsm
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m.submodules.sample_mem = sample_mem = self.sample_mem
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m.submodules.trig_blk = trig_blk = self.trig_blk
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# Concat all the probes together, and feed to input of sample memory
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# (it is necessary to reverse the order such that first probe occupies
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@ -173,11 +177,10 @@ class LogicAnalyzerCore(Elaboratable):
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trig_blk.bus_i.eq(self.fsm.bus_o),
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sample_mem.bus_i.eq(trig_blk.bus_o),
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self.bus_o.eq(sample_mem.bus_o),
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# Non-bus Connections
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fsm.trigger.eq(trig_blk.trig),
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sample_mem.user_addr.eq(fsm.r.write_pointer),
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sample_mem.user_we.eq(fsm.write_enable)
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sample_mem.user_we.eq(fsm.write_enable),
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]
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return m
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@ -215,6 +218,7 @@ class LogicAnalyzerCore(Elaboratable):
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print_if_verbose(" -> Resetting core...")
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state = self.fsm.r.get_probe("state")
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if state != self.fsm.states["IDLE"]:
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self.fsm.r.set_probe("request_start", 0)
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self.fsm.r.set_probe("request_stop", 0)
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self.fsm.r.set_probe("request_stop", 1)
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self.fsm.r.set_probe("request_stop", 0)
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@ -224,12 +228,16 @@ class LogicAnalyzerCore(Elaboratable):
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# Set triggers
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print_if_verbose(" -> Setting triggers...")
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self.trig_blk.set_triggers(self.config)
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self.trig_blk.clear_triggers()
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if self.config["trigger_mode"] != "immediate":
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self.trig_blk.set_triggers(self.config)
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# Set trigger mode, default to single-shot if user didn't specify a mode
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print_if_verbose(" -> Setting trigger mode...")
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if "trigger_mode" in self.config:
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self.fsm.r.set_probe("trigger_mode", self.config["trigger_mode"])
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mode = self.config["trigger_mode"].upper()
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self.fsm.r.set_probe("trigger_mode", self.fsm.trigger_modes[mode])
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else:
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self.fsm.r.set_probe("trigger_mode", self.fsm.trigger_modes["SINGLE_SHOT"])
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@ -244,6 +252,7 @@ class LogicAnalyzerCore(Elaboratable):
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# Send a start request to the state machine
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print_if_verbose(" -> Starting capture...")
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self.fsm.r.set_probe("request_start", 0)
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self.fsm.r.set_probe("request_start", 1)
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self.fsm.r.set_probe("request_start", 0)
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@ -362,16 +371,20 @@ class LogicAnalyzerCapture:
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signals.append(signal)
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clock = writer.register_var("manta", "clk", "wire", size=1)
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trigger = writer.register_var("manta", "trigger", "wire", size=1)
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# include a trigger signal such would be meaningful (ie, we didn't trigger immediately)
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if self.config["trigger_mode"] != "immediate":
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trigger = writer.register_var("manta", "trigger", "wire", size=1)
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# add the data to each probe in the vcd file
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for timestamp in range(0, 2 * len(self.data)):
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# run the clock
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writer.change(clock, timestamp, timestamp % 2 == 0)
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# set the trigger
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triggered = (timestamp // 2) >= self.get_trigger_location()
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writer.change(trigger, timestamp, triggered)
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# set the trigger (if there is one)
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if self.config["trigger_mode"] != "immediate":
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triggered = (timestamp // 2) >= self.get_trigger_location()
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writer.change(trigger, timestamp, triggered)
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# add other signals
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for signal in signals:
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@ -56,7 +56,7 @@ class LogicAnalyzerFSM(Elaboratable):
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def elaborate(self, platform):
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m = Module()
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m.submodules["registers"] = self.r
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m.submodules.registers = self.r
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prev_request_start = Signal(1)
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prev_request_stop = Signal(1)
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@ -74,6 +74,7 @@ class LogicAnalyzerFSM(Elaboratable):
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m.d.sync += self.write_enable.eq(1)
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with m.If(self.r.trigger_mode == self.trigger_modes["IMMEDIATE"]):
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m.d.sync += self.r.state.eq(self.states["CAPTURING"])
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m.d.sync += self.r.write_pointer.eq(self.r.write_pointer + 1)
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with m.Else():
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with m.If(self.r.trigger_location == 0):
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@ -82,7 +83,7 @@ class LogicAnalyzerFSM(Elaboratable):
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with m.Else():
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m.d.sync += self.r.state.eq(self.states["MOVE_TO_POSITION"])
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m.d.sync += self.r.state.eq(self.states["MOVE_TO_POSITION"])
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# m.d.sync += self.r.state.eq(self.states["MOVE_TO_POSITION"])
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with m.Elif(self.r.state == self.states["MOVE_TO_POSITION"]):
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m.d.sync += self.r.write_pointer.eq(self.r.write_pointer + 1)
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@ -38,7 +38,7 @@ class LogicAnalyzerPlayback(Elaboratable):
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def elaborate(self, platform):
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m = Module()
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m.submodules["mem"] = self.mem
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m.submodules.mem = self.mem
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m.d.comb += self.read_port.en.eq(1)
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@ -28,12 +28,13 @@ class LogicAnalyzerTriggerBlock(Elaboratable):
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def get_max_addr(self):
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return self.r.get_max_addr()
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def set_triggers(self, config):
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# reset all triggers to zero
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def clear_triggers(self):
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# reset all triggers to disabled with no argument
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for p in self.probes:
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self.r.set_probe(p.name + "_op", 0)
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self.r.set_probe(p.name + "_arg", 0)
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def set_triggers(self, config):
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# set triggers
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for trigger in config["triggers"]:
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components = trigger.strip().split(" ")
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@ -53,7 +54,7 @@ class LogicAnalyzerTriggerBlock(Elaboratable):
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m = Module()
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# Add IO Core as submodule
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m.submodules["registers"] = self.r
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m.submodules.registers = self.r
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# Add triggers as submodules
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for t in self.triggers:
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@ -126,7 +126,7 @@ class Manta(Elaboratable):
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m = Module()
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# Add interface as submodule
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m.submodules["interface"] = self.interface
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m.submodules.interface = self.interface
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# Add all cores as submodules
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for name, instance in self.cores.items():
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@ -61,7 +61,7 @@ class ReadOnlyMemoryCore(Elaboratable):
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m.d.sync += self.bus_pipe[0].eq(self.bus_i)
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for i in range(1, 3):
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m.d.sync += self.bus_pipe[i].eq(self.bus_pipe[i-1])
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m.d.sync += self.bus_pipe[i].eq(self.bus_pipe[i - 1])
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m.d.sync += self.bus_o.eq(self.bus_pipe[2])
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@ -232,10 +232,10 @@ class UARTInterface(Elaboratable):
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# fancy submoduling and such goes in here
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m = Module()
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m.submodules["uart_rx"] = uart_rx = UARTReceiver(self.clocks_per_baud)
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m.submodules["bridge_rx"] = bridge_rx = ReceiveBridge()
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m.submodules["bridge_tx"] = bridge_tx = TransmitBridge()
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m.submodules["uart_tx"] = uart_tx = UARTTransmitter(self.clocks_per_baud)
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m.submodules.uart_rx = uart_rx = UARTReceiver(self.clocks_per_baud)
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m.submodules.bridge_rx = bridge_rx = ReceiveBridge()
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m.submodules.bridge_tx = bridge_tx = TransmitBridge()
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m.submodules.uart_tx = uart_tx = UARTTransmitter(self.clocks_per_baud)
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m.d.comb += [
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# UART RX -> Internal Bus
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@ -13,7 +13,7 @@ class IOCoreLoopbackTest(Elaboratable):
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self.port = port
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self.config = self.platform_specific_config()
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self.m = Manta(self.config)
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self.manta = Manta(self.config)
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def platform_specific_config(self):
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return {
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@ -41,17 +41,17 @@ class IOCoreLoopbackTest(Elaboratable):
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def elaborate(self, platform):
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m = Module()
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m.submodules["manta"] = self.m
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m.submodules.manta = self.manta
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uart_pins = platform.request("uart")
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m.d.comb += [
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self.m.io_core.probe0.eq(self.m.io_core.probe4),
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self.m.io_core.probe1.eq(self.m.io_core.probe5),
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self.m.io_core.probe2.eq(self.m.io_core.probe6),
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self.m.io_core.probe3.eq(self.m.io_core.probe7),
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self.m.interface.rx.eq(uart_pins.rx.i),
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uart_pins.tx.o.eq(self.m.interface.tx),
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self.manta.io_core.probe0.eq(self.manta.io_core.probe4),
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self.manta.io_core.probe1.eq(self.manta.io_core.probe5),
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self.manta.io_core.probe2.eq(self.manta.io_core.probe6),
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self.manta.io_core.probe3.eq(self.manta.io_core.probe7),
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self.manta.interface.rx.eq(uart_pins.rx.i),
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uart_pins.tx.o.eq(self.manta.interface.tx),
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]
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return m
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@ -71,7 +71,7 @@ class IOCoreLoopbackTest(Elaboratable):
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outputs = self.config["cores"]["io_core"]["outputs"]
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for name, attrs in outputs.items():
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actual = self.m.io_core.get_probe(name)
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actual = self.manta.io_core.get_probe(name)
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if isinstance(attrs, dict):
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if "initial_value" in attrs:
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@ -100,8 +100,8 @@ class IOCoreLoopbackTest(Elaboratable):
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width = self.config["cores"]["io_core"]["inputs"][input]
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value = randint(0, 2**width - 1)
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self.m.io_core.set_probe(output, value)
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readback = self.m.io_core.get_probe(input)
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self.manta.io_core.set_probe(output, value)
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readback = self.manta.io_core.get_probe(input)
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if readback != value:
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raise ValueError(
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@ -12,7 +12,7 @@ class LogicAnalyzerCounterTest(Elaboratable):
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self.port = port
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self.config = self.platform_specific_config()
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self.m = Manta(self.config)
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self.manta = Manta(self.config)
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def platform_specific_config(self):
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return {
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@ -20,9 +20,8 @@ class LogicAnalyzerCounterTest(Elaboratable):
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"la": {
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"type": "logic_analyzer",
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"sample_depth": 1024,
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"trigger_location": 500,
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"trigger_mode": "immediate",
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"probes": {"larry": 1, "curly": 3, "moe": 9},
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"triggers": ["moe RISING"],
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},
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||||
},
|
||||
"uart": {
|
||||
|
|
@ -34,20 +33,20 @@ class LogicAnalyzerCounterTest(Elaboratable):
|
|||
|
||||
def elaborate(self, platform):
|
||||
m = Module()
|
||||
m.submodules["manta"] = self.m
|
||||
m.submodules.manta = self.manta
|
||||
uart_pins = platform.request("uart")
|
||||
|
||||
larry = self.m.la.probes[0]
|
||||
curly = self.m.la.probes[1]
|
||||
moe = self.m.la.probes[2]
|
||||
larry = self.manta.la.probes[0]
|
||||
curly = self.manta.la.probes[1]
|
||||
moe = self.manta.la.probes[2]
|
||||
|
||||
m.d.sync += larry.eq(larry + 1)
|
||||
m.d.sync += curly.eq(curly + 1)
|
||||
m.d.sync += moe.eq(moe + 1)
|
||||
|
||||
m.d.comb += [
|
||||
self.m.interface.rx.eq(uart_pins.rx.i),
|
||||
uart_pins.tx.o.eq(self.m.interface.tx),
|
||||
self.manta.interface.rx.eq(uart_pins.rx.i),
|
||||
uart_pins.tx.o.eq(self.manta.interface.tx),
|
||||
]
|
||||
|
||||
return m
|
||||
|
|
@ -57,7 +56,7 @@ class LogicAnalyzerCounterTest(Elaboratable):
|
|||
|
||||
def verify(self):
|
||||
self.build_and_program()
|
||||
cap = self.m.la.capture()
|
||||
cap = self.manta.la.capture()
|
||||
|
||||
# check that VCD export works
|
||||
cap.export_vcd("out.vcd")
|
||||
|
|
@ -66,7 +65,7 @@ class LogicAnalyzerCounterTest(Elaboratable):
|
|||
cap.export_playback_verilog("out.v")
|
||||
|
||||
# verify that each signal is just a counter modulo the width of the signal
|
||||
for name, width in self.m.la.config["probes"].items():
|
||||
for name, width in self.manta.la.config["probes"].items():
|
||||
trace = cap.get_trace(name)
|
||||
|
||||
for i in range(len(trace) - 1):
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@ class MemoryCoreLoopbackTest(Elaboratable):
|
|||
self.port = port
|
||||
|
||||
self.config = self.platform_specific_config()
|
||||
self.m = Manta(self.config)
|
||||
self.manta = Manta(self.config)
|
||||
|
||||
def platform_specific_config(self):
|
||||
return {
|
||||
|
|
@ -50,16 +50,16 @@ class MemoryCoreLoopbackTest(Elaboratable):
|
|||
|
||||
def elaborate(self, platform):
|
||||
m = Module()
|
||||
m.submodules["manta"] = self.m
|
||||
m.submodules.manta = self.manta
|
||||
|
||||
uart_pins = platform.request("uart")
|
||||
|
||||
m.d.comb += [
|
||||
self.m.mem_core.user_addr.eq(self.m.io_core.addr),
|
||||
self.m.mem_core.user_data.eq(self.m.io_core.data),
|
||||
self.m.mem_core.user_we.eq(self.m.io_core.we),
|
||||
self.m.interface.rx.eq(uart_pins.rx.i),
|
||||
uart_pins.tx.o.eq(self.m.interface.tx),
|
||||
self.manta.mem_core.user_addr.eq(self.manta.io_core.addr),
|
||||
self.manta.mem_core.user_data.eq(self.manta.io_core.data),
|
||||
self.manta.mem_core.user_we.eq(self.manta.io_core.we),
|
||||
self.manta.interface.rx.eq(uart_pins.rx.i),
|
||||
uart_pins.tx.o.eq(self.manta.interface.tx),
|
||||
]
|
||||
|
||||
return m
|
||||
|
|
@ -68,14 +68,14 @@ class MemoryCoreLoopbackTest(Elaboratable):
|
|||
self.platform.build(self, do_program=True)
|
||||
|
||||
def write_user_side(self, addr, data):
|
||||
self.m.io_core.set_probe("we", 0)
|
||||
self.m.io_core.set_probe("addr", addr)
|
||||
self.m.io_core.set_probe("data", data)
|
||||
self.m.io_core.set_probe("we", 1)
|
||||
self.m.io_core.set_probe("we", 0)
|
||||
self.manta.io_core.set_probe("we", 0)
|
||||
self.manta.io_core.set_probe("addr", addr)
|
||||
self.manta.io_core.set_probe("data", data)
|
||||
self.manta.io_core.set_probe("we", 1)
|
||||
self.manta.io_core.set_probe("we", 0)
|
||||
|
||||
def verify_register(self, addr, expected_data):
|
||||
data = self.m.mem_core.read_from_user_addr(addr)
|
||||
data = self.manta.mem_core.read_from_user_addr(addr)
|
||||
|
||||
if data != expected_data:
|
||||
raise ValueError(
|
||||
|
|
|
|||
Loading…
Reference in New Issue