rename Nexys A7 to Nexys 4 DDR

doc/repository_structure.md

@@ -2,7 +2,7 @@
 - `src/manta/` contains the Python source needed to generate and run the cores.
 - `test/` contains Manta's tests, which are a mix of functional simulations and hardware-in-the-loop testing. These tests leverage the `pytest` testing framework.
 - `doc/` contains the documentation you're reading right now!
-- `examples/` contains examples for both the Digilent Nexys 4 DDR/Nexys A7 with thier onboard Series-7, as well as the Icestick with its onboard iCE40.
+- `examples/` contains examples of Manta being used in designs for a handful of FPGA boards.
 - `.github/` contains GitHub Actions workflows for automatically running the tests and building the documentation site on every commit.
 
 ## Tools Used
@@ -12,4 +12,4 @@
 - [GitHub Actions](https://docs.github.com/en/actions) is used for continuous integration.
 
 ## GitHub Actions Setup
-Since Vivado is large and requires individual licenses, it is run on a private server, which is configured as a self-hosted runner in GitHub Actions. This is a virtual server hosted with KVM/QEMU and managed by libvirt, which is configured as transient so that it reloads its state from a snapshot periodically. A Nexys A7 and Icestick are connected to the physical machine and passthrough-ed to this VM so that continuous integration can check against real hardware.
+Since Vivado is large and requires individual licenses, it is run on a private server, which is configured as a self-hosted runner in GitHub Actions. This is a virtual server hosted with KVM/QEMU and managed by libvirt, which is configured as transient so that it reloads its state from a snapshot periodically. A Nexys4 DDR and Icestick are connected to the physical machine and passthrough-ed to this VM so that continuous integration can check against real hardware.

examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/top_level.xdc

@@ -3,7 +3,7 @@
 ## - uncomment the lines corresponding to used pins
 ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
 
-## This file has been modified from the default .xdc provided by Digilent for the Nexys A7
+## This file has been modified from the default .xdc provided by Digilent for the Nexys 4 DDR
 
 ## Clock signal - uncomment _both_ of these lines to create clk_100mhz
 set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk

examples/verilog/nexys4_ddr/uart_io_core/top_level.xdc

@@ -3,7 +3,7 @@
 ## - uncomment the lines corresponding to used pins
 ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
 
-## This file has been modified from the default .xdc provided by Digilent for the Nexys A7
+## This file has been modified from the default .xdc provided by Digilent for the Nexys 4 DDR
 
 ## Clock signal - uncomment _both_ of these lines to create clk_100mhz
 set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk

examples/verilog/nexys4_ddr/uart_logic_analyzer/top_level.xdc

@@ -3,7 +3,7 @@
 ## - uncomment the lines corresponding to used pins
 ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
 
-## This file has been modified from the default .xdc provided by Digilent for the Nexys A7
+## This file has been modified from the default .xdc provided by Digilent for the Nexys4 DDR
 
 ## Clock signal - uncomment _both_ of these lines to create clk_100mhz
 set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk

test/test_toolchains.py

@@ -6,7 +6,7 @@ import pytest
 
 
 @pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed")
-def test_arty_a7_tools():
+def test_nexys4_ddr_tools():
     Nexys4DDRPlatform().build(Blinky(), do_program=False)