Fischer Moseley
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357b7eed94
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refactor logic analyzer a little, add ps2_decoder example, and implement trigger_loc
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2023-04-18 01:06:39 -04:00 |
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Fischer Moseley
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870d299c74
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add docs and add trigger config for logic analyzer
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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3400ea63c8
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squash data duplication bug
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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f6f9096895
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add batch read/write UART for speedo mode
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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9cc2357ea4
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update command line positional args
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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7c1e4fc2c0
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add logic analyzer playback module auto-generation
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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9d8836bda3
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add prototype simulation replay
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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1c74d4a714
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add running the logic analyzer to the python API
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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7bec8b15c8
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fix bug that removed stop requests
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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a2ad90a66a
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modify sim and generator, seems to work in simulation
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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518f49cc29
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rewrite logic analyzer fsm
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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bdca8e01e7
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add boilerplate for new modules - just gotta rewrite the fsm
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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4d2c3d08e6
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fix line ending bug on windows
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2023-04-13 19:48:47 -04:00 |
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Fischer Moseley
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d8eeb65b8f
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fix pipelining in video_sprite exmaple
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2023-04-13 18:00:22 -04:00 |
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Fischer Moseley
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153ae7e3df
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video sprite example working! kinda frankensteined tho
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2023-04-13 17:02:55 -04:00 |
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Fischer Moseley
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4ece833ea1
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add video sprite example
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2023-04-12 20:03:22 -04:00 |
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Fischer Moseley
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5ceefc8da9
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this bram core has taken my soul
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2023-04-12 18:15:50 -04:00 |
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Fischer Moseley
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ba6100ce30
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import tutorial from yesterday, add mostly working bram core
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2023-04-12 11:47:50 -04:00 |
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Fischer Moseley
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12f498dc9a
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add cursed BRAM core implementation
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2023-04-10 14:38:29 -04:00 |
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Fischer Moseley
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353be7551e
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remove all narly verilog from python! 🤠
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2023-04-08 16:23:02 -04:00 |
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Fischer Moseley
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20957e5ba7
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refactor to separate verilog and python
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2023-04-08 14:07:08 -04:00 |
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Fischer Moseley
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f5bf1c6954
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update lut_ram to build on icestick. doesn't work on hardware yet, but doesn't break xilinx builds, so we're rolling with it
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2023-04-04 00:03:13 -04:00 |
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Fischer Moseley
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c604614428
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autogenerate logic_analyzer and sample_mem
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2023-04-03 23:15:09 -04:00 |
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Fischer Moseley
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0a4a1519c4
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clean up inferred BRAM, trim whitespace
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2023-04-03 21:20:58 -04:00 |
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Fischer Moseley
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aab1b5ac10
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add semi-working trigger block autogen
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2023-04-03 16:43:28 -04:00 |
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Fischer Moseley
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8f08dffc70
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consolidate logic analyzer testbench
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2023-04-03 12:20:24 -04:00 |
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Fischer Moseley
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f682e5386f
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add working hand-parameterized logic analyzer! still buggy but this is super neato 🤠
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2023-04-02 22:49:48 -04:00 |
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Fischer Moseley
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df4d243b9a
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refactor test structure
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2023-04-02 20:33:50 -04:00 |
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Fischer Moseley
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af295ead51
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logic analyzer appears to kinda work in simulation. buggy, but working!
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2023-04-02 13:54:34 -04:00 |
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Fischer Moseley
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edf94c9cf7
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add api generation tests
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2023-03-24 10:34:15 -04:00 |
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Fischer Moseley
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18fcbfe1f2
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add IO core example
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2023-03-23 23:15:55 -04:00 |
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Fischer Moseley
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c4b6358537
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clean up port autodetection
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2023-03-23 22:27:51 -04:00 |
Fischer Moseley
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a562c8136c
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add ability to autodetect serial port
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2023-03-23 20:46:49 -04:00 |
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Fischer Moseley
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f7077f96d8
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add lut ram operations to Python API
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2023-03-23 19:38:19 -04:00 |
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Fischer Moseley
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a57b5908f2
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add verbose output to serial
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2023-03-23 18:10:52 -04:00 |
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Fischer Moseley
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53c116a4f0
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add global address assignment
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2023-03-19 11:17:39 -06:00 |
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Fischer Moseley
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500267798f
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add example instantiation to top of autogenerated output
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2023-03-19 10:57:32 -06:00 |
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Fischer Moseley
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edd50168e2
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refactor IO core read/write to be less ugly
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2023-03-17 20:12:57 -04:00 |
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Fischer Moseley
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3cf5164d23
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add bus read/write to python
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2023-03-17 19:04:59 -04:00 |
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Fischer Moseley
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d46e833529
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can now successfully autogenerate and build io cores
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2023-03-16 12:13:46 -04:00 |
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Fischer Moseley
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2c51aa9a9a
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paritally imnplement io core autogeneration
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2023-03-16 09:38:17 -04:00 |
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Fischer Moseley
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bdc082e8d6
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add io core, playing with verilator lint
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2023-03-16 08:30:19 -04:00 |
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Fischer Moseley
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11495fca61
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refactor logic analyzer into submodules
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2023-03-15 22:43:21 -04:00 |
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Fischer Moseley
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fade794333
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add initialls logic_analyzer core
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2023-03-15 15:57:42 -04:00 |
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Fischer Moseley
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aa2ba43e8f
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rename lut mem to lut ram, add to manta generator
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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4d6df33921
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add site config to mkdocs
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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a6e7aa287d
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add top-level interface ports to top-level declaration
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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a5518c1873
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add core chain module self-wiring
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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f536488550
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add top level ports procedurally
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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3fda03ec90
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break up hdl definition into multiple member functinos
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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9dba38925b
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add module definitions to generated hdl
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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7d98988b87
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add autogenerated instantiations and connections for LA cores
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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f5f7f91bdc
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fix LogicAnalyzerCore instantiation from file
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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334aa8c005
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refactor __init__.py to be object-oriented
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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5e2f02ebd6
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add linting to makefile, update bus testbenches
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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4d9792702a
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clean up testbenches, add Makefile for sims
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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e022696b31
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add working example for macOS bug
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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a70ba2d0a8
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replace uart modules with zipcpu for testing, TX seems to misalign itself
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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70e2bd10e7
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rename, slightly patch bridge_tx
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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5454ed37e9
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add bus_tb, has nearly all of manta end-to-end
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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c1620871cf
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add lut memory and tests, still need to sort out pipelining
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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e55d919098
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add in bus architecture prototypes from the last few days
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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bd42850bf8
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use only ubuntu-latest for all tests
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2023-02-15 13:57:45 -05:00 |
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Fischer Moseley
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979f1591b6
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update data file paths
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2023-02-14 21:07:53 -05:00 |
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Fischer Moseley
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ad18b9263b
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i hate python packaging but everything works now
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2023-02-14 20:53:36 -05:00 |
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Fischer Moseley
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02fc53cbf7
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package for PyPI
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2023-02-14 17:14:39 -05:00 |
Fischer Moseley
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ae89e9a778
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rename files, remove reference to ILA
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2023-02-09 15:30:25 -05:00 |
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Fischer Moseley
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d2bcbe2418
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import from openILA
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2023-02-04 12:43:00 -05:00 |