add example instantiation to top of autogenerated output
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parent
edd50168e2
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7
Makefile
7
Makefile
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@ -60,5 +60,8 @@ clean:
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rm -rf dist/
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rm -rf src/mantaray.egg-info
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loc:
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find . -type f \( -iname \*.sv -o -iname \*.v -o -iname \*.py -o -iname \*.yaml -o -iname \*.md \) | sed 's/.*/"&"/' | xargs wc -l
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total_loc:
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find . -type f \( -iname \*.sv -o -iname \*.v -o -iname \*.py -o -iname \*.yaml -o -iname \*.yml -o -iname \*.md \) | sed 's/.*/"&"/' | xargs wc -l
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real_loc:
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find src test -type f \( -iname \*.sv -o -iname \*.v -o -iname \*.py -o -iname \*.yaml -o -iname \*.md \) | sed 's/.*/"&"/' | xargs wc -l
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@ -680,6 +680,57 @@ Provided under a GNU GPLv3 license. Go wild.
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*/
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"""
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return header
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def generate_ex_inst(self):
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# this is a C-style block comment that contains an instantiation
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# of the configured manta instance - the idea is that a user
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# can copy-paste that into their design instead of trying to spot
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# the difference between their code and the autogenerated code.
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# hopefully this saves time!
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# this turns a list like ['input wire foo', 'output reg bar'] into
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# a nice string like ".foo(foo),\n .bar(bar)"
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interface_ports = self.interface.hdl_top_level_ports()
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interface_ports = [port.split(',')[0] for port in interface_ports]
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interface_ports = [port.split(' ')[-1] for port in interface_ports]
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interface_ports = [f".{port}({port})" for port in interface_ports]
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interface_ports = [f" {port},\n" for port in interface_ports]
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interface_ports = "".join(interface_ports)
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core_chain_ports = []
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for core in self.cores:
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ports = [port.split(',')[0] for port in core.hdl_top_level_ports()]
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ports = [port.split(' ')[-1] for port in ports]
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ports = [f".{port}({port})" for port in ports]
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ports = [f" {port},\n" for port in ports]
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ports = "".join(ports)
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ports = "\n" + ports
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core_chain_ports.append(ports)
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core_chain_ports = "\n".join(core_chain_ports)
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ports = interface_ports + core_chain_ports
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# remove trailing comma
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ports = ports.rstrip()
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if ports[-1] == ",":
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ports = ports[:-1]
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return f"""
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/*
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// Here's an example instantiation of the Manta module you configured,
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// feel free to copy-paste this into your source!
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manta manta_inst (
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.clk(clk),
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{ports});
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*/
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"""
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def generate_declaration(self):
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# get all the top level connections for each module.
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@ -762,6 +813,9 @@ module manta (
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# generate header
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header = self.generate_header()
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# generate example instantiation
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ex_inst = self.generate_ex_inst()
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# generate module declaration
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declar = self.generate_declaration()
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@ -781,7 +835,7 @@ module manta (
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module_defs = self.generate_module_defs()
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# assemble all the parts
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hdl = header + declar + interface_rx + core_chain + interface_tx + footer
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hdl = header + ex_inst + declar + interface_rx + core_chain + interface_tx + footer
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hdl += "\n /* ---- Module Definitions ---- */\n"
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hdl += module_defs
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