fix LogicAnalyzerCore instantiation from file
This commit is contained in:
Fischer Moseley
parent
ca2579e471
commit
f5f7f91bdc
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@ -1,6 +1,7 @@
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---
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cores:
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logic_analyzer:
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my_logic_analyzer:
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type: logic_analyzer
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sample_depth: 4096
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probes:
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@ -9,16 +9,16 @@ version = "0.0.0"
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class UARTInterface:
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def __init__(self, config):
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# Obtain port. No way to check if it's valid yet.
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assert config["port"], "No serial port provided to UART core."
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assert "port" in config, "No serial port provided to UART core."
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self.port = config["port"]
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# Check that clock frequency is provided and positive
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assert config["clock_freq"], "Clock frequency not provided to UART core."
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assert "clock_freq" in config, "Clock frequency not provided to UART core."
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assert config["clock_freq"] > 0, "Clock frequency must be positive."
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self.clock_freq = config["clock_freq"]
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# Check that baudrate is provided and positive
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assert config["baudrate"], "Baudrate not provided to UART core."
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assert "baudrate" in config, "Baudrate not provided to UART core."
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assert config["baudrate"] > 0, "Baudrate must be positive."
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self.baudrate = config["baudrate"]
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@ -34,8 +34,8 @@ class UARTInterface:
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baudrate_error <= 5
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), "Unable to match target baudrate - they differ by {baudrate_error}%"
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def open(self):
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import serial
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self.ser = serial.Serial(self.port, self.baudrate)
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def read(self, bytes):
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@ -50,26 +50,27 @@ class UARTInterface:
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def rx_hdl(self):
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pkgutil.get_data(__name__, "rx_uart.sv").decode()
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class IOCore:
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def __init__(self, config, interface):
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self.interface = interface
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class LogicAnalyzerCore:
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def __init__(self, config, interface):
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self.interface = interface
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# load config
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assert config["sample_depth"], "Sample depth not found for logic analyzer core."
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assert "sample_depth" in config, "Sample depth not found for logic analyzer core."
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self.sample_depth = config["sample_depth"]
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assert config["probes"], "No probe definitions found."
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assert "probes" in config, "No probe definitions found."
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assert len(config["probes"]) > 0, "Must specify at least one probe."
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for probe in config["probes"]:
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assert (
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probe["width"] > 0
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), "Probe {probe} is of invalid width - it must be of at least width one."
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for probe_name, probe_width in config["probes"].items():
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assert probe_width > 0, f"Probe {probe_name} is of invalid width - it must be of at least width one."
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self.probes = config["probes"]
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assert config["triggers"], "No triggers found."
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assert "triggers" in config, "No triggers found."
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assert len(config["triggers"]) > 0, "Must specify at least one trigger."
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self.triggers = config["triggers"]
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@ -185,17 +186,37 @@ class Manta:
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def __init__(self, config_filepath):
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config = self.read_config_file(config_filepath)
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# TODO: figure out some better place to put the interface data.
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# it should probably go in it's own class. But for now it can go here.
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self.interface = self.get_interface(config)
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# set interface
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if "uart" in config:
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self.interface = UARTInterface(config["uart"])
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else:
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raise ValueError("Unrecognized interface specified.")
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# add cores to manta
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# check that cores were provided
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assert "cores" in config, "No cores found."
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assert len(config["cores"]) > 0, "Must specify at least one core."
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for core in config:
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if core == "LA":
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self.cores.append(LogicAnalyzerCore(core, self.interface))
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# add cores to self
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self.cores = []
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for i, core_name in enumerate(config["cores"]):
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core = config["cores"][core_name]
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# make sure a type was specified for this core
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assert "type" in core, f"No type specified for core {core_name}."
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# add the core to ourself
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if core["type"] == "logic_analyzer":
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new_core = LogicAnalyzerCore(core, self.interface)
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elif core["type"] == "io":
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new_core = IOCore(core, self.interface)
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else:
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raise ValueError(f"Unrecognized core type specified for {core_name}.")
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# add friendly name, so users can do Manta.my_logic_analyzer.read() for example
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setattr(self, core_name, new_core)
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self.cores.append(new_core)
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def read_config_file(self, path):
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"""Take path to configuration file, and retun the configuration as a python list/dict object."""
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@ -218,30 +239,47 @@ class Manta:
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return config
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def get_interface(self, config):
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if "uart" in config:
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return UARTInterface(config["uart"])
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elif "ethernet" in config:
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raise NotImplementedError("Ethernet not supported yet!")
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elif "jtag" in config:
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raise NotImplementedError("JTAG not supported yet!")
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else:
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raise ValueError("Interface not recognized")
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def generate(self):
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# this occurs in two steps: generating manta and the top-level,
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# and pasting in all the HDL from earlier.
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cores_hdl = {core.name: core.generate for core in self.cores}
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uart_rx_hdl = pkgutil.get_data(__name__, "rx_uart.sv").decode()
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bridge_rx_hdl = pkgutil.get_data(__name__, "bridge_rx.sv").decode()
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bridge_tx_hdl = pkgutil.get_data(__name__, "bridge_tx.sv").decode()
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uart_tx_hdl = pkgutil.get_data(__name__, "uart_tx.sv").decode()
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# make pairwise cores
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core_pairs = [(cores[i-1], cores[i]) for i in range(1, len(cores))]
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# write HDL to instantiate and connect them
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connections = []
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for src, dest in core_pairs:
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# wait who's source and who's destination? have to know both the src, dest,
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# and also current core at any given moment
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# so then is the solution src src_current current current_dst dst
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hdl = src.inst()
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hdl += hdl.replace(".addr_i()", f".addr_i({src}_{dest}_addr)")
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hdl += hdl.replace(".wdata_i()", f".wdata_i({src}_{dest}_wdata)")
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hdl += hdl.replace(".rdata_i()", f".rdata_i({src}_{dest}_rdata)")
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hdl += hdl.replace(".rw_i()", f".rw_i({src}_{dest}_rw)")
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hdl += hdl.replace(".valid_i()", f".valid_i({src}_{dest}_valid)")
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hdl += "\n"
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hdl += f"reg[15:0] {src}_{dest}_addr\n"
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hdl += f"reg[15:0] {src}_{dest}_wdata\n"
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hdl += f"reg[15:0] {src}_{dest}_rdata\n"
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hdl += f"reg {src}_{dest}_rw\n"
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hdl += f"reg {src}_{dest}_valid\n\n"
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connections.append(hdl)
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# write HDL to instantiate them, now that we know src and dest
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instantiations = []
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for core in cores:
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hdl = core.inst()
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hdl = hdl.replace(".addr_i()", f".addr_i({src}_{dest}_addr)")
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hdl = hdl.replace(".addr_i()", f".addr_i({src}_{dest}_addr)")
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# for core in cores:
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# registers = ''
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# registers += f'{core}{}'
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