Fischer Moseley
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03a3ec6c9f
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update logic analyzer capture method
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2024-01-05 22:11:49 -08:00 |
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Fischer Moseley
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958ccadbd0
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refactored logic analyzer working in sim
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2024-01-05 21:43:53 -08:00 |
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Fischer Moseley
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a11605b2b7
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refactor logic analyzer
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2024-01-05 16:50:25 -08:00 |
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Fischer Moseley
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ee18e10ae1
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add immediate capture mode to logic analyzer
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2024-01-03 13:35:09 -07:00 |
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Fischer Moseley
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07ae9cc2e8
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get playback module from class method
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2023-12-31 20:07:47 -08:00 |
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Fischer Moseley
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d31aa2650e
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switch playback to synchronous read ports, make things synthesizable
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2023-12-28 21:46:44 -08:00 |
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Fischer Moseley
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90a5dba665
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finish playback module pipelining
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2023-12-28 19:20:06 -08:00 |
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Fischer Moseley
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9867e369cb
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update playback module, needs pipelining
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2023-12-28 17:57:21 -08:00 |
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Fischer Moseley
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34f6a54330
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fix integer bounds, move to self-hosted runner
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2023-12-28 15:30:55 -08:00 |
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Fischer Moseley
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0eddf12931
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banish .DS_Store
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2023-12-28 14:27:59 -08:00 |
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Fischer Moseley
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bc616fd3bf
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inital source, imported from splat
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2023-12-28 14:22:29 -08:00 |
Andi Qu
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096b5ff515
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Fix integer bounds
This bug was causing our 6.2050 project to fail lmao
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2023-11-27 22:50:57 -05:00 |
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Fischer Moseley
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a1130e8424
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update docs in response to feedback from Joe
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2023-09-11 19:09:42 -07:00 |
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Fischer Moseley
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c427cee010
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fix missing f in f-string
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2023-09-11 17:06:39 -07:00 |
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Fischer Moseley
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b4fb79bc8e
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add write/readback tests, seems to pass
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2023-09-04 23:03:49 -04:00 |
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Fischer Moseley
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0bbdf4faa6
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make io_core python api ready for test
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2023-09-04 23:03:49 -04:00 |
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Fischer Moseley
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060583d8fc
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add working io_core autogeneration
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2023-09-04 23:03:49 -04:00 |
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Fischer Moseley
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6b035ff40b
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update logic analyzer capture to pull from multiple addresses
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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3d722d1e60
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fix nasty addressing bug in block_memory
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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44a8c57dc5
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swap to zipcpu uart_rx
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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5065d2ce2b
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update naming convention
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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9e20ba5609
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update ports command to handle macOS
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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f9472cf11b
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fix bug in core chain generation
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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c1ae6b5339
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fix (hopefully) last deprecated API call, thanks again Joe :)
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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f902d07b1d
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update read responses to use D as preamble
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2023-09-02 11:39:16 -04:00 |
Fischer Moseley
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4b9d941bc5
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fix API call that doesn't exist anymore, thanks Joe :)
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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4abc2e2cae
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update template naming for consistency
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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56b2442df7
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move uart code for verification to test/
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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d580419a5b
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remove lut_mem, clean up examples
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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112bd43963
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remove mention of wdata/rdata
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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2b483b1beb
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add bridge_rx formal to makefile
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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ac23e8a599
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make functional sim run again
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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25b2ff0dd0
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add first round of tweaks to bridge_rx_tb
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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1a536080f1
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rewrite bridge_rx and add basic formal
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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9771d80fd1
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replace logic nettype with reg
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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38f7ee86fa
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add uart_rx and refactor uart_tx and bridge_tx
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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f5caca613a
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simplify uart/ether APIs, improve lazy loading
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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cef5e9318b
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flip i and j, and see the light
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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15aa5f469f
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add ethernet_tx_tb
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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2c461ed08d
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add working ethernet_tx testbench
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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9c5ea31d14
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enforce consistent naming of lut_mem module
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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54b97fd120
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add working ethernet verilog autogeneration woot woot :)
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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2013e74f0f
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update help message with consistent version number
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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b3d402c1f5
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refactor python/hdl structure
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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7cd8a2cfa5
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tidy up mac stack
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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8e139bba3a
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add working l2 mac in hardware - need to fix ethertype to get scapy to play nice
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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c507f795f1
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add ethernet_tx/rx, semi-working in hardware
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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cfddb67652
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add warnings for unrecognized parameters in configuration
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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a2d14116de
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add trigger_mode register to logic analyzer core
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2023-04-18 23:14:41 -04:00 |
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Fischer Moseley
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c1894dac73
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add signal to vcd export to signal when triggered
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2023-04-18 01:22:01 -04:00 |