refactor test structure

.github/workflows/functional_sim.yml

@@ -1,4 +1,4 @@
-name: functional_simulation
+name: functional_sim
 on: [push]
 jobs:
   all:
@@ -6,4 +6,4 @@ jobs:
     steps:
       - uses: actions/checkout@v3
       - run: sudo apt install iverilog
-      - run: make sim 
+      - run: make functional_sim

Makefile

@@ -15,59 +15,59 @@ total_loc:
 	find . -type f \( -iname \*.sv -o -iname \*.v -o -iname \*.py -o -iname \*.yaml -o -iname \*.yml -o -iname \*.md \) | sed 's/.*/"&"/' | xargs  wc -l
 
 real_loc:
-	find src ${TB} -type f \( -iname \*.sv -o -iname \*.v -o -iname \*.py -o -iname \*.yaml -o -iname \*.md \) | sed 's/.*/"&"/' | xargs  wc -l
+	find src test -type f \( -iname \*.sv -o -iname \*.v -o -iname \*.py -o -iname \*.yaml -o -iname \*.md \) | sed 's/.*/"&"/' | xargs  wc -l
 
-test: api_gen func_sim
+test: auto_gen functional_sim
 
 # API Generation Tests
-api_gen: 
-	python3 test/api_gen/run_test.py
+auto_gen: 
+	python3 test/auto_gen/run_tests.py
 
 # Functional Simulation
-func_sim: io_core_tb logic_analyzer_tb bit_fifo_tb bridge_rx_tb bridge_tx_tb fifo_tb lut_ram_tb uart_tb uart_tx_tb 
+functional_sim: io_core_tb logic_analyzer_tb bit_fifo_tb bridge_rx_tb bridge_tx_tb fifo_tb lut_ram_tb uart_tb uart_tx_tb 
 
 io_core_tb:
-	iverilog -g2012 -o sim.out -y src/manta test/hdl_tb/io_core_tb.sv
+	iverilog -g2012 -o sim.out -y src/manta test/functional_sim/io_core_tb.sv
 	vvp sim.out
 	rm sim.out
 
 logic_analyzer_tb:
-	iverilog -g2012 -o sim.out -y src/manta test/hdl_tb/logic_analyzer_tb.sv
+	iverilog -g2012 -o sim.out -y src/manta test/functional_sim/logic_analyzer_tb.sv
 	vvp sim.out
 	rm sim.out
 
 bit_fifo_tb:
-	iverilog -g2012 -o sim.out -y src/manta test/hdl_tb/bit_fifo_tb.sv
+	iverilog -g2012 -o sim.out -y src/manta test/functional_sim/bit_fifo_tb.sv
 	vvp sim.out
 	rm sim.out
 
 bridge_rx_tb:
-	iverilog -g2012 -o sim.out -y src/manta test/hdl_tb/bridge_rx_tb.sv
+	iverilog -g2012 -o sim.out -y src/manta test/functional_sim/bridge_rx_tb.sv
 	vvp sim.out
 	rm sim.out
 
 bridge_tx_tb:
-	iverilog -g2012 -o sim.out -y src/manta test/hdl_tb/bridge_tx_tb.sv
+	iverilog -g2012 -o sim.out -y src/manta test/functional_sim/bridge_tx_tb.sv
 	vvp sim.out
 	rm sim.out
 
 fifo_tb:
-	iverilog -g2012 -o sim.out -y src/manta test/hdl_tb/fifo_tb.sv 
+	iverilog -g2012 -o sim.out -y src/manta test/functional_sim/fifo_tb.sv 
 	vvp sim.out >> /dev/null # this one is noisy right now
 	rm sim.out
 
 lut_ram_tb:
-	iverilog -g2012 -o sim.out -y src/manta test/hdl_tb/lut_ram_tb.sv
+	iverilog -g2012 -o sim.out -y src/manta test/functional_sim/lut_ram_tb.sv
 	vvp sim.out
 	rm sim.out
 
 uart_tb:
-	iverilog -g2012 -o sim.out -y src/manta test/hdl_tb/uart_tb.sv
+	iverilog -g2012 -o sim.out -y src/manta test/functional_sim/uart_tb.sv
 	vvp sim.out
 	rm sim.out
 
 uart_tx_tb:
-	iverilog -g2012 -o sim.out -y src/manta test/hdl_tb/uart_tx_tb.sv
+	iverilog -g2012 -o sim.out -y src/manta test/functional_sim/uart_tx_tb.sv
 	vvp sim.out
 	rm sim.out
 	

src/manta/__init__.py

@@ -9,10 +9,7 @@ class UARTInterface:
     def __init__(self, config):
         # Obtain port. Try to automatically detect port if "auto" is specified
         assert "port" in config, "No serial port provided to UART core."
-
         self.port = config["port"]
-        if config["port"] == "auto":
-            self.port = self.autodetect_port()
 
         # Check that clock frequency is provided and positive
         assert "clock_freq" in config, "Clock frequency not provided to UART core."
@@ -42,6 +39,9 @@ class UARTInterface:
             self.verbose = config["verbose"]
 
     def open_port_if_not_alredy_open(self):
+        if self.port == "auto":
+            self.port = self.autodetect_port()
+
         if not hasattr(self, "ser"):
             import serial
             self.ser = serial.Serial(self.port, self.baudrate)
@@ -53,8 +53,8 @@ class UARTInterface:
         recognized_devices = []
         for port in serial.tools.list_ports.comports():
             if (port.vid == 0x403) and (port.pid == 0x6010):
-                recognized_devices.append(port)     
-        
+                recognized_devices.append(port)
+
         # board manufacturers seem to always make the 0th serial
         # interface on the FT2232 be for programming over JTAG,
         # and then the 1st to be for UART. as a result, we always

test/auto_gen/run_tests.py

@@ -7,8 +7,11 @@ from manta import Manta
 
 # Valid Configurations
 
+# test that they make a python API without errors
+# test that their verilog passes lint
+
 print(" ==== Testing valid configurations ====")
-valid_configs_path = 'test/api_gen/valid_configs/'
+valid_configs_path = 'test/auto_gen/valid_configs/'
 for config_file in sorted(listdir(valid_configs_path)):
     caught_exception = None
     try:
@@ -29,8 +32,10 @@ print('\n')
 
 # Invalid Configurations
 
+# test that they throw errors when generating a python API
+
 print(" ==== Testing invalid configurations ====")
-invalid_configs_path = 'test/api_gen/invalid_configs/'
+invalid_configs_path = 'test/auto_gen/invalid_configs/'
 for config_file in sorted(listdir(invalid_configs_path)):
     caught_exception = None
     try: