add core chain module self-wiring
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Fischer Moseley
parent
f536488550
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a5518c1873
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@ -69,7 +69,6 @@ class UARTInterface:
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.o_wr(urx_brx_axiv),
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.o_data(urx_brx_axid));
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// uart_rx --> bridge_rx signals
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logic [7:0] urx_brx_axid;
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logic urx_brx_axiv;
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@ -163,7 +162,7 @@ class LogicAnalyzerCore:
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.wdata_o(),
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.rdata_o(),
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.rw_o(),
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.valid_o());\n\n"""
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.valid_o());\n"""
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return hdl
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@ -375,22 +374,32 @@ class Manta:
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hdl = core.hdl_inst()
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# connect input
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if (i == 0):
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src_name = "brx"
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else:
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src_name = self.cores[i-1].name
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hdl = hdl.replace(".addr_i()", f".addr_i({src_name}_{core.name}_addr)")
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hdl = hdl.replace(".wdata_i()", f".wdata_i({src_name}_{core.name}_wdata)")
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hdl = hdl.replace(".rdata_i()", f".rdata_i({src_name}_{core.name}_rdata)")
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hdl = hdl.replace(".rw_i()", f".rw_i({src_name}_{core.name}_rw)")
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hdl = hdl.replace(".valid_i()", f".valid_i({src_name}_{core.name}_valid)")
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# connect output
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if (i < len(self.cores)-1):
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dst = self.cores[i+1]
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dst_name = self.cores[i+1]
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else:
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dst_name = "btx"
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hdl = hdl.replace(".addr_o()", f".addr_o({core.name}_{dst.name}_addr)")
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hdl = hdl.replace(".wdata_o()", f".wdata_o({core.name}_{dst.name}_wdata)")
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hdl = hdl.replace(".rdata_o()", f".rdata_o({core.name}_{dst.name}_rdata)")
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hdl = hdl.replace(".rw_o()", f".rw_o({core.name}_{dst.name}_rw)")
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hdl = hdl.replace(".valid_o()", f".valid_o({core.name}_{dst.name}_valid)")
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if (i > 0):
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src = self.cores[i-1]
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hdl = hdl.replace(".addr_i()", f".addr_i({src.name}_{core.name}_addr)")
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hdl = hdl.replace(".wdata_i()", f".wdata_i({src.name}_{core.name}_wdata)")
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hdl = hdl.replace(".rdata_i()", f".rdata_i({src.name}_{core.name}_rdata)")
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hdl = hdl.replace(".rw_i()", f".rw_i({src.name}_{core.name}_rw)")
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hdl = hdl.replace(".valid_i()", f".valid_i({src.name}_{core.name}_valid)")
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hdl = hdl.replace(".addr_o()", f".addr_o({core.name}_{dst_name}_addr)")
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hdl = hdl.replace(".wdata_o()", f".wdata_o({core.name}_{dst_name}_wdata)")
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hdl = hdl.replace(".rdata_o()", f".rdata_o({core.name}_{dst_name}_rdata)")
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hdl = hdl.replace(".rw_o()", f".rw_o({core.name}_{dst_name}_rw)")
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hdl = hdl.replace(".valid_o()", f".valid_o({core.name}_{dst_name}_valid)")
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insts.append(hdl)
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@ -441,30 +450,40 @@ module manta (
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"""
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def generate_interface_rx(self):
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interface_rx = self.interface.rx_hdl_inst()
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# instantiate interface_rx, substitute in register names
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interface_rx_inst = self.interface.rx_hdl_inst()
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interface_rx_inst = interface_rx_inst.replace("addr_o()", f"addr_o(brx_{self.cores[0].name}_addr)")
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interface_rx_inst = interface_rx_inst.replace("wdata_o()", f"wdata_o(brx_{self.cores[0].name}_wdata)")
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interface_rx_inst = interface_rx_inst.replace("rw_o()", f"rw_o(brx_{self.cores[0].name}_rw)")
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interface_rx_inst = interface_rx_inst.replace("valid_o()", f"valid_o(brx_{self.cores[0].name}_valid)")
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# connect interface_rx to core_chain
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interface_rx_chain_connection = f"""
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interface_rx_conn= f"""
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reg [15:0] brx_{self.cores[0].name}_addr;
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reg [15:0] brx_{self.cores[0].name}_wdata;
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reg brx_{self.cores[0].name}_rw;
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reg brx_{self.cores[0].name}_valid;\n"""
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interface_rx = interface_rx.replace("addr_o()", f"addr_o(brx_{self.cores[0].name}_addr)")
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interface_rx = interface_rx.replace("wdata_o()", f"wdata_o(brx_{self.cores[0].name}_wdata)")
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interface_rx = interface_rx.replace("rw_o()", f"rw_o(brx_{self.cores[0].name}_rw)")
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interface_rx = interface_rx.replace("valid_o()", f"valid_o(brx_{self.cores[0].name}_valid)")
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return interface_rx
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return interface_rx_inst + interface_rx_conn
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def generate_interface_tx(self):
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interface_tx = self.interface.tx_hdl_inst()
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interface_tx = interface_tx.replace("addr_i()", f"addr_o({self.cores[0].name}_btx_addr)")
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interface_tx = interface_tx.replace("rdata_i()", f"rdata_o({self.cores[0].name}_btx_rdata)")
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interface_tx = interface_tx.replace("rw_i()", f"rw_o({self.cores[0].name}_btx_rw)")
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interface_tx = interface_tx.replace("valid_i()", f"valid_o({self.cores[0].name}_btx_valid)")
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# connect core_chain to interface_tx
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interface_tx_conn = f"""
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reg [15:0] {self.cores[-1].name}_btx_rdata;
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reg {self.cores[-1].name}_btx_rw;
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reg {self.cores[-1].name}_btx_valid;\n"""
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# instantiate interface_tx, substitute in register names
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interface_tx_inst = self.interface.tx_hdl_inst()
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interface_tx_inst = interface_tx_inst.replace("addr_i()", f"addr_o({self.cores[0].name}_btx_addr)")
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interface_tx_inst = interface_tx_inst.replace("rdata_i()", f"rdata_o({self.cores[0].name}_btx_rdata)")
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interface_tx_inst = interface_tx_inst.replace("rw_i()", f"rw_o({self.cores[0].name}_btx_rw)")
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interface_tx_inst = interface_tx_inst.replace("valid_i()", f"valid_o({self.cores[0].name}_btx_valid)")
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return interface_tx
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return interface_tx_conn + interface_tx_inst
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def generate_footer(self):
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return """endmodule\n"""
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