add autogenerated instantiations and connections for LA cores
This commit is contained in:
Fischer Moseley
parent
8c645a5115
commit
7d98988b87
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@ -36,6 +36,7 @@ class UARTInterface:
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def open(self):
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import serial
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self.ser = serial.Serial(self.port, self.baudrate)
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def read(self, bytes):
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@ -50,29 +51,54 @@ class UARTInterface:
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def rx_hdl(self):
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pkgutil.get_data(__name__, "rx_uart.sv").decode()
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class IOCore:
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def __init__(self, config, interface):
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self.interface = interface
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class LogicAnalyzerCore:
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def __init__(self, config, interface):
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self.interface = interface
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# load config
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assert "sample_depth" in config, "Sample depth not found for logic analyzer core."
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assert (
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"sample_depth" in config
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), "Sample depth not found for logic analyzer core."
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self.sample_depth = config["sample_depth"]
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assert "probes" in config, "No probe definitions found."
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assert len(config["probes"]) > 0, "Must specify at least one probe."
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for probe_name, probe_width in config["probes"].items():
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assert probe_width > 0, f"Probe {probe_name} is of invalid width - it must be of at least width one."
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assert (
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probe_width > 0
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), f"Probe {probe_name} is of invalid width - it must be of at least width one."
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self.probes = config["probes"]
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assert "triggers" in config, "No triggers found."
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assert len(config["triggers"]) > 0, "Must specify at least one trigger."
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self.triggers = config["triggers"]
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def inst(self):
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hdl = f"""
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la_core {self.name} (
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.clk(),
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.addr_i(),
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.wdata_i(),
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.rdata_i(),
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.rw_i(),
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.valid_i(),
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.addr_o(),
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.wdata_o(),
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.rdata_o(),
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.rw_o(),
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.valid_o());\n\n"""
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return hdl
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def run(self):
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self.interface.open()
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@ -186,13 +212,13 @@ class Manta:
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def __init__(self, config_filepath):
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config = self.read_config_file(config_filepath)
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# set interface
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if "uart" in config:
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# set interface
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if "uart" in config:
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self.interface = UARTInterface(config["uart"])
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else:
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raise ValueError("Unrecognized interface specified.")
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# check that cores were provided
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# check that cores were provided
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assert "cores" in config, "No cores found."
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assert len(config["cores"]) > 0, "Must specify at least one core."
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@ -202,18 +228,21 @@ class Manta:
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core = config["cores"][core_name]
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# make sure a type was specified for this core
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assert "type" in core, f"No type specified for core {core_name}."
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assert "type" in core, f"No type specified for core {core_name}."
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# add the core to ourself
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if core["type"] == "logic_analyzer":
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new_core = LogicAnalyzerCore(core, self.interface)
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elif core["type"] == "io":
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new_core = IOCore(core, self.interface)
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else:
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raise ValueError(f"Unrecognized core type specified for {core_name}.")
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# TODO: update class defs so that we don't monkey-patch like this. this is not good. i am lazy
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setattr(new_core, 'name', core_name)
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# add friendly name, so users can do Manta.my_logic_analyzer.read() for example
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setattr(self, core_name, new_core)
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self.cores.append(new_core)
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@ -239,59 +268,96 @@ class Manta:
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return config
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def generate_connections(self):
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# generates hdl for registers that connect two modules together
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# make pairwise cores
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core_pairs = [(self.cores[i - 1], self.cores[i]) for i in range(1, len(self.cores))]
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conns = []
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for core_pair in core_pairs:
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src = core_pair[0].name
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dst = core_pair[1].name
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hdl = f"\treg [15:0] {src}_{dst}_addr;\n"
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hdl += f"\treg [15:0] {src}_{dst}_wdata;\n"
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hdl += f"\treg [15:0] {src}_{dst}_rdata;\n"
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hdl += f"\treg {src}_{dst}_rw;\n"
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hdl += f"\treg {src}_{dst}_valid;\n"
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conns.append(hdl)
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return conns
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def generate_instantiations(self):
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# generates hdl for modules that need to be connected together
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insts = []
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for i, core in enumerate(self.cores):
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# should probably check if core is LogicAnalyzerCore or IOCore
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hdl = core.inst()
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if (i < len(self.cores)-1):
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dst = self.cores[i+1]
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hdl = hdl.replace(".addr_o()", f".addr_o({core.name}_{dst.name}_addr)")
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hdl = hdl.replace(".wdata_o()", f".wdata_o({core.name}_{dst.name}_wdata)")
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hdl = hdl.replace(".rdata_o()", f".rdata_o({core.name}_{dst.name}_rdata)")
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hdl = hdl.replace(".rw_o()", f".rw_o({core.name}_{dst.name}_rw)")
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hdl = hdl.replace(".valid_o()", f".valid_o({core.name}_{dst.name}_valid)")
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if (i > 0):
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src = self.cores[i-1]
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hdl = hdl.replace(".addr_i()", f".addr_i({src.name}_{core.name}_addr)")
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hdl = hdl.replace(".wdata_i()", f".wdata_i({src.name}_{core.name}_wdata)")
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hdl = hdl.replace(".rdata_i()", f".rdata_i({src.name}_{core.name}_rdata)")
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hdl = hdl.replace(".rw_i()", f".rw_i({src.name}_{core.name}_rw)")
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hdl = hdl.replace(".valid_i()", f".valid_i({src.name}_{core.name}_valid)")
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insts.append(hdl)
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return insts
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def generate(self):
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# this occurs in two steps: generating manta and the top-level,
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# and pasting in all the HDL from earlier.
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uart_rx_hdl = pkgutil.get_data(__name__, "rx_uart.sv").decode()
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bridge_rx_hdl = pkgutil.get_data(__name__, "bridge_rx.sv").decode()
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bridge_tx_hdl = pkgutil.get_data(__name__, "bridge_tx.sv").decode()
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uart_tx_hdl = pkgutil.get_data(__name__, "uart_tx.sv").decode()
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uart_rx_hdl = pkgutil.get_data(__name__, "rx_uart.v").decode()
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bridge_rx_hdl = pkgutil.get_data(__name__, "bridge_rx.v").decode()
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bridge_tx_hdl = pkgutil.get_data(__name__, "bridge_tx.v").decode()
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uart_tx_hdl = pkgutil.get_data(__name__, "uart_tx.v").decode()
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# make pairwise cores
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core_pairs = [(cores[i-1], cores[i]) for i in range(1, len(cores))]
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# write HDL to instantiate and connect them
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connections = []
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for src, dest in core_pairs:
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# wait who's source and who's destination? have to know both the src, dest,
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# and also current core at any given moment
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"""
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ok so the way this works is that we have two lists, instantiations and connections
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we make connections first, and it works by pairwise iterating over pairs of cores and
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doing the 'reg[N:0] src_dest_name' thing
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# so then is the solution src src_current current current_dst dst
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hdl = src.inst()
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hdl += hdl.replace(".addr_i()", f".addr_i({src}_{dest}_addr)")
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hdl += hdl.replace(".wdata_i()", f".wdata_i({src}_{dest}_wdata)")
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hdl += hdl.replace(".rdata_i()", f".rdata_i({src}_{dest}_rdata)")
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hdl += hdl.replace(".rw_i()", f".rw_i({src}_{dest}_rw)")
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hdl += hdl.replace(".valid_i()", f".valid_i({src}_{dest}_valid)")
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once we have that, we then generate the instantiations. we iterate through the same pairs,
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setting outputs on the src, and inputs on the dest. this leaves the inputs of the first node
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and the outputs of the last node unconnected, but we'll have a final step to take care of that.
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"""
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hdl += "\n"
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hdl += f"reg[15:0] {src}_{dest}_addr\n"
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hdl += f"reg[15:0] {src}_{dest}_wdata\n"
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hdl += f"reg[15:0] {src}_{dest}_rdata\n"
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hdl += f"reg {src}_{dest}_rw\n"
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hdl += f"reg {src}_{dest}_valid\n\n"
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connections.append(hdl)
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# write HDL to instantiate them, now that we know src and dest
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instantiations = []
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for core in cores:
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hdl = core.inst()
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hdl = hdl.replace(".addr_i()", f".addr_i({src}_{dest}_addr)")
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hdl = hdl.replace(".addr_i()", f".addr_i({src}_{dest}_addr)")
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# for core in cores:
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# registers = ''
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# registers += f'{core}{}'
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# # wire cores together
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# add preamble to top of file
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user = os.environ.get("USER", os.environ.get("USERNAME"))
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timestamp = datetime.now().strftime("%d %b %Y at %H:%M:%S")
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hdl = "This manata definitinon was autogenerated on {timestamp} by {user}\n\n"
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hdl += "If this breaks or if you've got dank formal verification memes,\n"
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hdl += "please contact fischerm [at] mit.edu\n"
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hdl = f"/* This manata definition was generated on {timestamp} by {user}\n"
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hdl += " *\n"
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hdl += " * If this breaks or if you've got dank formal verification memes,\n"
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hdl += " * please contact fischerm [at] mit.edu\n"
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hdl += " */\n"
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insts = self.generate_instantiations()
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conns = self.generate_connections()
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for i, inst in enumerate(insts):
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hdl += inst
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if (i != len(insts)-1):
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hdl += conns[i]
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return hdl
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def main():
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