refactor IO core read/write to be less ugly
This commit is contained in:
Fischer Moseley
parent
3cf5164d23
commit
edd50168e2
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@ -1,6 +1,5 @@
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## IO Core
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- test examples that build
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- update IO core read/write memory handling to be less ugly
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- add logic for ports >16 bits in width
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- clock domain crossing
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- figure out what happens for module naming - it's possible we could have two modules that have the same ports but have different names
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@ -21,6 +20,7 @@
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- write interface
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## Python API
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- implement global address assignment
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- find a better way of handling tabs
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- make finding a serial port possible even if no cores are configured
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- make autodetecting and automatically selecting a serial device possible
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@ -2,7 +2,7 @@
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`timescale 1ns/1ps
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/*
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This manta definition was generated on 16 Mar 2023 at 12:07:39 by fischerm
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This manta definition was generated on 17 Mar 2023 at 20:02:55 by fischerm
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If this breaks or if you've got dank formal verification memes,
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please contact fischerm [at] mit.edu
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@ -418,31 +418,31 @@ always @(posedge clk) begin
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if(!rw_i) begin // reads
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case (addr_i)
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BASE_ADDR + 0: rdata_o <= {15'b0, btnu};
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BASE_ADDR + 1: rdata_o <= {15'b0, btnd};
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BASE_ADDR + 2: rdata_o <= {15'b0, btnl};
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BASE_ADDR + 3: rdata_o <= {15'b0, btnr};
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BASE_ADDR + 4: rdata_o <= {15'b0, btnc};
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BASE_ADDR + 5: rdata_o <= sw;
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BASE_ADDR + 6: rdata_o <= led;
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BASE_ADDR + 7: rdata_o <= {15'b0, led16_b};
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BASE_ADDR + 8: rdata_o <= {15'b0, led16_g};
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BASE_ADDR + 9: rdata_o <= {15'b0, led16_r};
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BASE_ADDR + 10: rdata_o <= {15'b0, led17_b};
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BASE_ADDR + 11: rdata_o <= {15'b0, led17_g};
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BASE_ADDR + 12: rdata_o <= {15'b0, led17_r};
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0: rdata_o <= {15'b0, btnu};
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1: rdata_o <= {15'b0, btnd};
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2: rdata_o <= {15'b0, btnl};
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3: rdata_o <= {15'b0, btnr};
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4: rdata_o <= {15'b0, btnc};
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5: rdata_o <= sw;
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6: rdata_o <= led;
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7: rdata_o <= {15'b0, led16_b};
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8: rdata_o <= {15'b0, led16_g};
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9: rdata_o <= {15'b0, led16_r};
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10: rdata_o <= {15'b0, led17_b};
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11: rdata_o <= {15'b0, led17_g};
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12: rdata_o <= {15'b0, led17_r};
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endcase
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end
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else begin // writes
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case (addr_i)
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BASE_ADDR + 6: led <= wdata_i;
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BASE_ADDR + 7: led16_b <= wdata_i[0];
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BASE_ADDR + 8: led16_g <= wdata_i[0];
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BASE_ADDR + 9: led16_r <= wdata_i[0];
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BASE_ADDR + 10: led17_b <= wdata_i[0];
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BASE_ADDR + 11: led17_g <= wdata_i[0];
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BASE_ADDR + 12: led17_r <= wdata_i[0];
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6: led <= wdata_i;
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7: led16_b <= wdata_i[0];
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8: led16_g <= wdata_i[0];
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9: led16_r <= wdata_i[0];
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10: led17_b <= wdata_i[0];
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11: led17_g <= wdata_i[0];
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12: led17_r <= wdata_i[0];
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endcase
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end
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end
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@ -131,91 +131,80 @@ class UARTInterface:
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.tx(tx));\n"""
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class IOCoreProbe:
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def __init__(self, name, width, direction, base_addr, interface):
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self.name = name
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self.width = width
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self.direction = direction
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self.base_addr = base_addr
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self.interface = interface
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def set(self, data):
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# check that value is within range for the width of the probe
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assert isinstance(data, int), "Data must be an integer."
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if data > 0:
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assert data <= (2**self.width) - 1, f"Unsigned value too large for probe of width {self.width}"
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elif data < 0:
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assert data >= -(2**(self.width-1))-1, f"Signed value too large for probe of width {self.width}"
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assert data <= (2**(self.width-1))-1, f"Signed value too large for probe of width {self.width}"
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self.interface.write_register(self.base_addr, data)
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def get(self, probe):
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return self.interface.read_register(self.base_addr)
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class IOCore:
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def __init__(self, config, interface):
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def __init__(self, config, name, base_addr, interface):
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self.name = name
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self.base_addr = base_addr
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self.interface = interface
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# make sure we have ports defined
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assert ('inputs' in config) or ('outputs' in config), "No input or output ports specified."
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# add inputs to core
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address = 0
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self.inputs = []
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# add input probes to core
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self.probes = []
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probe_base_addr = self.base_addr
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if 'inputs' in config:
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for name, width in config["inputs"].items():
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for name, width in config["inputs"].items():
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# make sure inputs are of reasonable width
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assert width > 0, f"Input {name} must have width greater than zero."
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assert isinstance(width, int), f"Probe {name} must have integer width."
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assert width > 0, f"Probe {name} must have positive width."
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self.inputs.append( {"name": name, "width": width, "address": address} )
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self.max_rel_addr = address
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address += 1
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probe = IOCoreProbe(name, width, "input", probe_base_addr, self.interface)
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# add friendly name, so users can do Manta.my_io_core.my_probe.set() for example
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setattr(self, name, probe)
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self.probes.append(probe)
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# add outputs to core
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self.outputs = []
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self.max_probe_addr = probe_base_addr
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probe_base_addr += 1
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# add output probes to core
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if 'outputs' in config:
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for name, width in config["outputs"].items():
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# make sure inputs are of reasonable width
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assert width > 0, f"Output {name} must have width greater than zero."
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assert isinstance(width, int), f"Probe {name} must have integer width."
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assert width > 0, f"Probe {name} must have positive width."
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probe = IOCoreProbe(name, width, "output", probe_base_addr, self.interface)
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# add friendly name, so users can do Manta.my_io_core.my_probe.set() for example
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setattr(self, name, probe)
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self.probes.append(probe)
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self.outputs.append( {"name": name, "width": width, "address": address} )
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self.max_rel_addr = address
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address += 1
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self.max_probe_addr = probe_base_addr
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probe_base_addr += 1
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def set(self, probe, data):
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# check that probe actually exists
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assert (probe in self.inputs) or (probe in self.outputs), "Probe {probe} not found."
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if probe in self.inputs:
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probe_def = self.inputs[probe]
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elif probe in self.outputs:
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probe_def = self.outputs[probe]
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# check that value is reasonable
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# (should be an integer between 0 and 2^width - 1)
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# send message
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addr = probe_def["address"] + self.base_addr
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assert isinstance(data, int), "Data must be an integer."
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if data > 0:
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assert data <= (2**probe_def["width"]) - 1, f"Unsigned value too large for probe of width {probe_def['width']}"
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elif data < 0:
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assert data >= -(2**(probe_def["width"]-1))-1, f"Signed value too large for probe of width {probe_def['width']}"
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assert data <= (2**(probe_def["width"]-1))-1, f"Signed value too large for probe of width {probe_def['width']}"
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self.interface.write_register(addr, data)
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def get(self, probe):
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# check that probe actually exists
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assert (probe in self.inputs) or (probe in self.outputs), "Probe {probe} not found."
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if probe in self.inputs:
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probe_def = self.inputs[probe]
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elif probe in self.outputs:
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probe_def = self.outputs[probe]
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addr = self.base_addr + probe_def["address"]
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return self.interface.read_register(addr)
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def hdl_inst(self):
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inst_ports = ""
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for input in self.inputs:
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name = input["name"]
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inst_ports += f".{name}({name}),\n "
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for output in self.outputs:
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name = output["name"]
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inst_ports += f".{name}({name}),\n "
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# TODO: make this a string comprehension
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inst_ports = [f".{probe.name}({probe.name}),\n " for probe in self.probes]
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inst_ports = "".join(inst_ports)
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inst_ports = inst_ports.rstrip()
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inst = f"""
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return f"""
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{self.name} {self.name}_inst(
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.clk(clk),
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@ -237,12 +226,9 @@ class IOCore:
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.valid_o()
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);
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"""
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return inst
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def hdl_def(self):
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# generate declaration
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top_level_ports = ',\n '.join(self.hdl_top_level_ports())
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top_level_ports += ','
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declaration = f"""
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@ -269,43 +255,29 @@ module {self.name} (
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"""
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# generate memory handling
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# TODO: clean this up, should just do all the probes at once
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# instead of splitting by input/output
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read_case_statement_body = ""
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for input in self.inputs:
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name = input["name"]
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width = input["width"]
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address = input["address"]
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if width == 16:
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read_case_statement_body += f"\t\t\t\t\tBASE_ADDR + {address}: rdata_o <= {name};\n"
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else:
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read_case_statement_body += f"\t\t\t\t\tBASE_ADDR + {address}: rdata_o <= {{{16-width}'b0, {name}}};\n"
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write_case_statement_body = ""
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for output in self.outputs:
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name = output["name"]
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width = output["width"]
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address = output["address"]
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for probe in self.probes:
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if width == 16:
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read_case_statement_body += f"\t\t\t\t\tBASE_ADDR + {address}: rdata_o <= {name};\n"
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else:
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read_case_statement_body += f"\t\t\t\t\tBASE_ADDR + {address}: rdata_o <= {{{16-width}'b0, {name}}};\n"
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if width == 1:
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write_case_statement_body += f"\t\t\t\t\tBASE_ADDR + {address}: {name} <= wdata_i[0];\n"
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elif width == 16:
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write_case_statement_body += f"\t\t\t\t\tBASE_ADDR + {address}: {name} <= wdata_i;\n"
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# add to read block
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if probe.width == 16:
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read_case_statement_body += f"\t\t\t\t\t{probe.base_addr}: rdata_o <= {probe.name};\n"
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else:
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write_case_statement_body += f"\t\t\t\t\tBASE_ADDR + {address}: {name} <= wdata_i[{width-1}:0];\n"
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read_case_statement_body += f"\t\t\t\t\t{probe.base_addr}: rdata_o <= {{{16-probe.width}'b0, {probe.name}}};\n"
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# if output, add to write block
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if probe.direction == "output":
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if probe.width == 1:
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write_case_statement_body += f"\t\t\t\t\t{probe.base_addr}: {probe.name} <= wdata_i[0];\n"
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elif probe.width == 16:
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write_case_statement_body += f"\t\t\t\t\t{probe.base_addr}: {probe.name} <= wdata_i;\n"
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else:
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write_case_statement_body += f"\t\t\t\t\t{probe.base_addr}: {probe.name} <= wdata_i[{probe.width-1}:0];\n"
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# remove trailing newline
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read_case_statement_body = read_case_statement_body.rstrip()
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write_case_statement_body = write_case_statement_body.rstrip()
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@ -322,7 +294,7 @@ always @(posedge clk) begin
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// check if address is valid
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if( (valid_i) && (addr_i >= BASE_ADDR) && (addr_i <= BASE_ADDR + {self.max_rel_addr})) begin
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if( (valid_i) && (addr_i >= BASE_ADDR) && (addr_i <= BASE_ADDR + {self.max_probe_addr})) begin
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if(!rw_i) begin // reads
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case (addr_i)
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@ -343,34 +315,18 @@ always @(posedge clk) begin
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return hdl
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def hdl_top_level_ports(self):
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probes = []
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# generate inputs
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for input in self.inputs:
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name = input["name"]
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width = input["width"]
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if width == 1:
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probes.append(f"input wire {name}")
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else:
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probes.append(f"input wire [{width-1}:0] {name}")
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# generate outputs
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for output in self.outputs:
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name = output["name"]
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width = output["width"]
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if width == 1:
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probes.append(f"output reg {name}")
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else:
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probes.append(f"output reg [{width-1}:0] {name}")
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return probes
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ports = []
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for probe in self.probes:
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net_type = "input wire " if probe.direction == "input" else "output reg "
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name_def = probe.name if probe.width == 1 else f"[{probe.width-1}:0] {probe.name}"
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ports.append(net_type + name_def)
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return ports
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class LUTRAMCore:
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def __init__(self, config, interface):
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def __init__(self, config, name, base_addr, interface):
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self.name = name
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self.base_addr = base_addr
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self.interface = interface
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assert "size" in config, "Size not specified for LUT RAM core."
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@ -404,7 +360,9 @@ class LUTRAMCore:
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return []
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class LogicAnalyzerCore:
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def __init__(self, config, interface):
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def __init__(self, config, name, base_addr, interface):
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self.name = name
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self.base_addr = base_addr
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self.interface = interface
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# load config
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@ -587,6 +545,7 @@ class Manta:
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assert len(config["cores"]) > 0, "Must specify at least one core."
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# add cores to self
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base_addr = 0 # TODO: implement address assignment
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self.cores = []
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for i, core_name in enumerate(config["cores"]):
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core = config["cores"][core_name]
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@ -596,20 +555,17 @@ class Manta:
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# add the core to ourself
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if core["type"] == "logic_analyzer":
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new_core = LogicAnalyzerCore(core, self.interface)
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new_core = LogicAnalyzerCore(core, core_name, base_addr, self.interface)
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elif core["type"] == "io":
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new_core = IOCore(core, self.interface)
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new_core = IOCore(core, core_name, base_addr, self.interface)
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elif core["type"] == "lut_ram":
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new_core = LUTRAMCore(core, self.interface)
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new_core = LUTRAMCore(core, core_name, base_addr, self.interface)
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else:
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raise ValueError(f"Unrecognized core type specified for {core_name}.")
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# TODO: update class defs so that we don't monkey-patch like this. this is not good. i am lazy
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setattr(new_core, 'name', core_name)
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# add friendly name, so users can do Manta.my_logic_analyzer.read() for example
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setattr(self, core_name, new_core)
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self.cores.append(new_core)
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