add module definitions to generated hdl
This commit is contained in:
Fischer Moseley
parent
7d98988b87
commit
9dba38925b
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@ -0,0 +1,471 @@
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`default_nettype none
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`timescale 1ns/1ps
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/* This manata definition was generated on 08 Mar 2023 at 21:04:09 by fischerm
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*
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* If this breaks or if you've got dank formal verification memes,
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* please contact fischerm [at] mit.edu
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*/
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rx_uart #(.CLOCKS_PER_BAUD(868)) urx (
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.i_clk(clk),
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.i_uart_rx(tb_urx_rxd),
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.o_wr(urx_brx_axiv),
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.o_data(urx_brx_axid));
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// uart_rx --> bridge_rx signals
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logic [7:0] urx_brx_axid;
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logic urx_brx_axiv;
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bridge_rx brx (
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.clk(clk),
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.rx_data(urx_brx_axid),
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.rx_valid(urx_brx_axiv),
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.addr_o(),
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.wdata_o(),
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.rw_o(),
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.valid_o());
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la_core my_logic_analyzer (
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.clk(),
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.addr_i(),
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.wdata_i(),
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.rdata_i(),
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.rw_i(),
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.valid_i(),
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.addr_o(),
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.wdata_o(),
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.rdata_o(),
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.rw_o(),
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.valid_o());
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bridge_tx btx (
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.clk(clk),
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.rdata_i(),
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.rw_i(),
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.valid_i(),
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.ready_i(utx_btx_ready),
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.data_o(btx_utx_data),
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.valid_o(btx_utx_valid));
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logic utx_btx_ready;
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logic btx_utx_valid;
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logic [7:0] btx_utx_data;
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uart_tx #(.CLOCKS_PER_BAUD(868)) utx (
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.clk(clk),
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.data(btx_utx_data),
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.valid(btx_utx_valid),
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.ready(utx_btx_ready),
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.tx(utx_tb_tx));
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endmodule
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/* ---- Module Definitions ---- */
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////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: rxuart.v
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//
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// Project: Verilog Tutorial Example file
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//
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// Purpose: Receives a character from a UART (serial port) wire. Key
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// features of this core include:
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//
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// - The baud rate is constant, and set by the CLOCKS_PER_BAUD parameter.
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// To be successful, one baud interval must be (approximately)
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// equal to CLOCKS_PER_BAUD / CLOCK_RATE_HZ seconds long.
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//
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// - The protocol used is the basic 8N1: 8 data bits, 1 stop bit, and no
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// parity.
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//
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// - This core has no reset
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// - This core has no error detection for frame errors
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// - This core cannot detect, report, or even recover from, a break
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// condition on the line. A break condition is defined as a
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// period of time where the i_uart_rx line is held low for longer
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// than one data byte (10 baud intervals)
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//
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// - There's no clock rate detection in this core
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//
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// Perhaps one of the nicer features of this core is that it (can be)
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// formally verified. It depends upon a separate (formally verified)
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// transmit core for this purpose.
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//
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// As with the other cores within this tutorial, there may (or may not) be
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// bugs within this design for you to find.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Written and distributed by Gisselquist Technology, LLC
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//
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// This program is hereby granted to the public domain.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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module rx_uart(
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input wire i_clk,
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input wire i_uart_rx,
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output reg o_wr,
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output reg [7:0] o_data);
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parameter [15:0] CLOCKS_PER_BAUD = 868;
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localparam [3:0] IDLE = 4'h0;
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localparam [3:0] BIT_ZERO = 4'h1;
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// localparam [3:0] BIT_ONE = 4'h2;
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// localparam [3:0] BIT_TWO = 4'h3;
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// localparam [3:0] BIT_THREE = 4'h4;
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// localparam [3:0] BIT_FOUR = 4'h5;
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// localparam [3:0] BIT_FIVE = 4'h6;
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// localparam [3:0] BIT_SIX = 4'h7;
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// localparam [3:0] BIT_SEVEN = 4'h8;
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localparam [3:0] STOP_BIT = 4'h9;
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reg [3:0] state;
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reg [15:0] baud_counter;
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reg zero_baud_counter;
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// 2FF Synchronizer
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//
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reg ck_uart;
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reg q_uart;
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initial { ck_uart, q_uart } = -1;
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always @(posedge i_clk)
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{ ck_uart, q_uart } <= { q_uart, i_uart_rx };
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initial state = IDLE;
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initial baud_counter = 0;
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always @(posedge i_clk)
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if (state == IDLE) begin
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state <= IDLE;
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baud_counter <= 0;
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if (!ck_uart) begin
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state <= BIT_ZERO;
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baud_counter <= CLOCKS_PER_BAUD+CLOCKS_PER_BAUD/2-1'b1;
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end
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end
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else if (zero_baud_counter) begin
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state <= state + 1;
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baud_counter <= CLOCKS_PER_BAUD-1'b1;
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if (state == STOP_BIT) begin
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state <= IDLE;
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baud_counter <= 0;
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end
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end
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else baud_counter <= baud_counter - 1'b1;
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always @(*)
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zero_baud_counter = (baud_counter == 0);
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always @(posedge i_clk)
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if ((zero_baud_counter)&&(state != STOP_BIT))
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o_data <= { ck_uart, o_data[7:1] };
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initial o_wr = 1'b0;
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always @(posedge i_clk)
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o_wr <= ((zero_baud_counter)&&(state == STOP_BIT));
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endmodule
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module bridge_rx(
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input wire clk,
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input wire[7:0] rx_data,
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input wire rx_valid,
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output reg[15:0] addr_o,
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output reg[15:0] wdata_o,
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output reg rw_o,
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output reg valid_o
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);
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// this is a hack, the FSM needs to be updated
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// but this will bypass it for now
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parameter ready_i = 1;
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parameter ADDR_WIDTH = 0;
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parameter DATA_WIDTH = 0;
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localparam PREAMBLE = 8'h4D;
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localparam CR = 8'h0D;
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localparam LF = 8'h0A;
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localparam ACQUIRE = 0;
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localparam TRANSMIT = 1;
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localparam ERROR = 2;
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reg [1:0] state;
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reg [3:0] bytes_received;
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// no global resets!
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initial begin
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addr_o = 0;
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wdata_o = 0;
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rw_o = 0;
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valid_o = 0;
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bytes_received = 0;
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state = ACQUIRE;
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end
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reg [3:0] rx_data_decoded;
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reg rx_data_is_0_thru_9;
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reg rx_data_is_A_thru_F;
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always @(*) begin
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rx_data_is_0_thru_9 = (rx_data >= 8'h30) & (rx_data <= 8'h39);
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rx_data_is_A_thru_F = (rx_data >= 8'h41) & (rx_data <= 8'h46);
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if (rx_data_is_0_thru_9) rx_data_decoded = rx_data - 8'h30;
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else if (rx_data_is_A_thru_F) rx_data_decoded = rx_data - 8'h41 + 'd10;
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else rx_data_decoded = 0;
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end
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always @(posedge clk) begin
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if (state == ACQUIRE) begin
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if(rx_valid) begin
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if (bytes_received == 0) begin
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if(rx_data == PREAMBLE) bytes_received <= 1;
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end
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else if( (bytes_received >= 1) & (bytes_received <= 4) ) begin
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// only advance if byte is valid hex digit
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if(rx_data_is_0_thru_9 | rx_data_is_A_thru_F) begin
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addr_o <= (addr_o << 4) | rx_data_decoded;
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bytes_received <= bytes_received + 1;
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end
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else state <= ERROR;
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end
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else if( bytes_received == 5) begin
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if( (rx_data == CR) | (rx_data == LF)) begin
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valid_o <= 1;
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rw_o = 0;
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bytes_received <= 0;
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state <= TRANSMIT;
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end
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else if (rx_data_is_0_thru_9 | rx_data_is_A_thru_F) begin
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bytes_received <= bytes_received + 1;
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wdata_o <= (wdata_o << 4) | rx_data_decoded;
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end
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else state <= ERROR;
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end
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else if ( (bytes_received >= 6) & (bytes_received <= 8) ) begin
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if (rx_data_is_0_thru_9 | rx_data_is_A_thru_F) begin
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wdata_o <= (wdata_o << 4) | rx_data_decoded;
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bytes_received <= bytes_received + 1;
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end
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else state <= ERROR;
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end
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else if (bytes_received == 9) begin
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bytes_received <= 0;
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if( (rx_data == CR) | (rx_data == LF)) begin
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valid_o <= 1;
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rw_o <= 1;
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state <= TRANSMIT;
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end
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else state <= ERROR;
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end
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end
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end
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else if (state == TRANSMIT) begin
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if(ready_i) begin
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valid_o <= 0;
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state <= ACQUIRE;
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end
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if(rx_valid) begin
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if ( (rx_data != CR) & (rx_data != LF)) begin
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valid_o <= 0;
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state <= ERROR;
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end
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end
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end
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end
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endmodule
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module bridge_tx(
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input wire clk,
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input wire [15:0] rdata_i,
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input wire rw_i,
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input wire valid_i,
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output reg [7:0] data_o,
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input wire ready_i,
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output reg valid_o);
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localparam PREAMBLE = 8'h4D;
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localparam CR = 8'h0D;
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localparam LF = 8'h0A;
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logic busy;
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logic [15:0] buffer;
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logic [3:0] byte_counter;
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initial begin
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busy = 0;
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buffer = 0;
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byte_counter = 0;
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valid_o = 0;
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end
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always @(posedge clk) begin
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if (!busy) begin
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if (valid_i && !rw_i) begin
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busy <= 1;
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buffer <= rdata_i;
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byte_counter <= 0;
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valid_o <= 1;
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end
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end
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if (busy) begin
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if(ready_i) begin
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byte_counter <= byte_counter + 1;
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if (byte_counter > 5) begin
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byte_counter <= 0;
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// stop transmitting if we don't have both valid and read
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if ( !(valid_i && !rw_i) ) begin
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busy <= 0;
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valid_o <= 0;
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end
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end
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end
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end
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end
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always @(*) begin
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case (byte_counter)
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0: data_o = PREAMBLE;
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1: data_o = (buffer[15:12] < 10) ? (buffer[15:12] + 8'h30) : (buffer[15:12] + 8'h41 - 'd10);
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2: data_o = (buffer[11:8] < 10) ? (buffer[11:8] + 8'h30) : (buffer[11:8] + 8'h41 - 'd10);
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3: data_o = (buffer[7:4] < 10) ? (buffer[7:4] + 8'h30) : (buffer[7:4] + 8'h41 - 'd10);
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4: data_o = (buffer[3:0] < 10) ? (buffer[3:0] + 8'h30) : (buffer[3:0] + 8'h41 - 'd10);
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5: data_o = CR;
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6: data_o = LF;
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default: data_o = 0;
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endcase
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end
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endmodule
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module uart_tx(
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input wire clk,
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input wire [7:0] data,
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input wire valid,
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output reg busy,
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output reg ready,
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output reg tx);
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// this transmitter only works with 8N1 serial, at configurable baudrate
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parameter CLOCKS_PER_BAUD = 868;
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reg [9:0] baud_counter;
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reg [8:0] data_buf;
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reg [3:0] bit_index;
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initial begin
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baud_counter = CLOCKS_PER_BAUD;
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data_buf = 0;
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bit_index = 0;
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busy = 0;
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ready = 1;
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tx = 1;
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end
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always @(posedge clk) begin
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if (valid && !busy) begin
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data_buf <= {1'b1, data};
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bit_index <= 0;
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tx <= 0; //wafflestomp that start bit
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baud_counter <= CLOCKS_PER_BAUD - 1;
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busy <= 1;
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ready <= 0;
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end
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else if (busy) begin
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baud_counter <= baud_counter - 1;
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ready <= (baud_counter == 1) && (bit_index == 9);
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if (baud_counter == 0) begin
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baud_counter <= CLOCKS_PER_BAUD - 1;
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if (bit_index == 9) begin
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if(valid) begin
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data_buf <= {1'b1, data};
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bit_index <= 0;
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tx <= 0;
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end
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else begin
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busy <= 0;
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ready <= 1;
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end
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// if valid happens here then we should bool
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end
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else begin
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tx <= data_buf[bit_index];
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bit_index <= bit_index + 1;
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end
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end
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end
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end
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endmodule
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`default_nettype wire
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@ -43,13 +43,68 @@ class UARTInterface:
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self.ser.read(bytes)
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def write(self, bytes):
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self.ser.write(bytes)
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self.ser.write(bytes)
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def tx_hdl(self):
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pkgutil.get_data(__name__, "uart_tx.sv").decode()
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def rx_hdl_def(self):
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uart_rx_def = pkgutil.get_data(__name__, "rx_uart.v").decode()
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bridge_rx_def = pkgutil.get_data(__name__, "bridge_rx.v").decode()
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return uart_rx_def + '\n' + bridge_rx_def
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def rx_hdl(self):
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pkgutil.get_data(__name__, "rx_uart.sv").decode()
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def tx_hdl_def(self):
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uart_tx_def = pkgutil.get_data(__name__, "uart_tx.v").decode()
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bridge_tx_def = pkgutil.get_data(__name__, "bridge_tx.v").decode()
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return bridge_tx_def + '\n' + uart_tx_def
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def rx_hdl_inst(self):
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return f"""
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rx_uart #(.CLOCKS_PER_BAUD({self.clocks_per_baud})) urx (
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.i_clk(clk),
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.i_uart_rx(tb_urx_rxd),
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.o_wr(urx_brx_axiv),
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.o_data(urx_brx_axid));
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// uart_rx --> bridge_rx signals
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logic [7:0] urx_brx_axid;
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logic urx_brx_axiv;
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bridge_rx brx (
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.clk(clk),
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.rx_data(urx_brx_axid),
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.rx_valid(urx_brx_axiv),
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.addr_o(),
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.wdata_o(),
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.rw_o(),
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.valid_o());
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"""
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def tx_hdl_inst(self):
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return f"""
|
||||
bridge_tx btx (
|
||||
.clk(clk),
|
||||
|
||||
.rdata_i(),
|
||||
.rw_i(),
|
||||
.valid_i(),
|
||||
|
||||
.ready_i(utx_btx_ready),
|
||||
.data_o(btx_utx_data),
|
||||
.valid_o(btx_utx_valid));
|
||||
|
||||
logic utx_btx_ready;
|
||||
logic btx_utx_valid;
|
||||
logic [7:0] btx_utx_data;
|
||||
|
||||
uart_tx #(.CLOCKS_PER_BAUD({self.clocks_per_baud})) utx (
|
||||
.clk(clk),
|
||||
|
||||
.data(btx_utx_data),
|
||||
.valid(btx_utx_valid),
|
||||
.ready(utx_btx_ready),
|
||||
|
||||
.tx(utx_tb_tx));
|
||||
"""
|
||||
|
||||
|
||||
class IOCore:
|
||||
|
|
@ -81,7 +136,7 @@ class LogicAnalyzerCore:
|
|||
assert len(config["triggers"]) > 0, "Must specify at least one trigger."
|
||||
self.triggers = config["triggers"]
|
||||
|
||||
def inst(self):
|
||||
def hdl_inst(self):
|
||||
hdl = f"""
|
||||
la_core {self.name} (
|
||||
.clk(),
|
||||
|
|
@ -171,7 +226,7 @@ class LogicAnalyzerCore:
|
|||
writer.change(probe, timestamp, val)
|
||||
vcd_file.close()
|
||||
|
||||
def hdl(self):
|
||||
def hdl_def(self):
|
||||
# Return an autogenerated verilog module definition for the core.
|
||||
# load source files
|
||||
tmpl = pkgutil.get_data(__name__, "la_template.v").decode()
|
||||
|
|
@ -179,13 +234,13 @@ class LogicAnalyzerCore:
|
|||
# add triggers
|
||||
trigger = [f"({trigger})" for trigger in self.triggers]
|
||||
trigger = " || ".join(trigger)
|
||||
templ = templ.replace("@TRIGGER", trigger)
|
||||
tmpl = tmpl.replace("@TRIGGER", trigger)
|
||||
|
||||
# add concat
|
||||
concat = [name for name in self.probes]
|
||||
concat = ", ".join(concat)
|
||||
concat = "{" + concat + "}"
|
||||
templ = templ.replace("@CONCAT", concat)
|
||||
tmpl = tmpl.replace("@CONCAT", concat)
|
||||
|
||||
# add probes
|
||||
probe_verilog = []
|
||||
|
|
@ -295,7 +350,7 @@ class Manta:
|
|||
for i, core in enumerate(self.cores):
|
||||
# should probably check if core is LogicAnalyzerCore or IOCore
|
||||
|
||||
hdl = core.inst()
|
||||
hdl = core.hdl_inst()
|
||||
|
||||
if (i < len(self.cores)-1):
|
||||
dst = self.cores[i+1]
|
||||
|
|
@ -318,45 +373,78 @@ class Manta:
|
|||
|
||||
return insts
|
||||
|
||||
def generate(self):
|
||||
# this occurs in two steps: generating manta and the top-level,
|
||||
# and pasting in all the HDL from earlier.
|
||||
|
||||
uart_rx_hdl = pkgutil.get_data(__name__, "rx_uart.v").decode()
|
||||
bridge_rx_hdl = pkgutil.get_data(__name__, "bridge_rx.v").decode()
|
||||
bridge_tx_hdl = pkgutil.get_data(__name__, "bridge_tx.v").decode()
|
||||
uart_tx_hdl = pkgutil.get_data(__name__, "uart_tx.v").decode()
|
||||
|
||||
|
||||
def generate_hdl(self):
|
||||
"""
|
||||
ok so the way this works is that we have two lists, instantiations and connections
|
||||
we make connections first, and it works by pairwise iterating over pairs of cores and
|
||||
doing the 'reg[N:0] src_dest_name' thing
|
||||
anatomy of manta.v:
|
||||
|
||||
once we have that, we then generate the instantiations. we iterate through the same pairs,
|
||||
setting outputs on the src, and inputs on the dest. this leaves the inputs of the first node
|
||||
and the outputs of the last node unconnected, but we'll have a final step to take care of that.
|
||||
- header
|
||||
- top-level module:
|
||||
- module declaration
|
||||
- top <-> cores
|
||||
- interface_in (for uart, this would be uart_rx and bridge_rx)
|
||||
|
||||
- core chain
|
||||
- core inst
|
||||
- core connection
|
||||
- core inst
|
||||
- core connection
|
||||
....
|
||||
|
||||
- interface_out (for uart, this is bridge_tx and uart_tx)
|
||||
- footer
|
||||
|
||||
|
||||
then come all the module definitions
|
||||
"""
|
||||
|
||||
|
||||
# add preamble to top of file
|
||||
# generate header
|
||||
user = os.environ.get("USER", os.environ.get("USERNAME"))
|
||||
timestamp = datetime.now().strftime("%d %b %Y at %H:%M:%S")
|
||||
|
||||
hdl = f"/* This manata definition was generated on {timestamp} by {user}\n"
|
||||
hdl += " *\n"
|
||||
hdl += " * If this breaks or if you've got dank formal verification memes,\n"
|
||||
hdl += " * please contact fischerm [at] mit.edu\n"
|
||||
hdl += " */\n"
|
||||
header = f"/* This manata definition was generated on {timestamp} by {user}\n"
|
||||
header += " *\n"
|
||||
header += " * If this breaks or if you've got dank formal verification memes,\n"
|
||||
header += " * please contact fischerm [at] mit.edu\n"
|
||||
header += " */\n"
|
||||
|
||||
# generate interface_rx
|
||||
interface_rx = self.interface.rx_hdl_inst()
|
||||
|
||||
# generate chain of cores
|
||||
insts = self.generate_instantiations()
|
||||
conns = self.generate_connections()
|
||||
core_chain = []
|
||||
for i, inst in enumerate(insts):
|
||||
hdl += inst
|
||||
core_chain.append(inst)
|
||||
|
||||
if (i != len(insts)-1):
|
||||
hdl += conns[i]
|
||||
core_chain.append(conns[i])
|
||||
|
||||
core_chain = '\n'.join(core_chain)
|
||||
|
||||
# generate interface_tx
|
||||
interface_tx = self.interface.tx_hdl_inst()
|
||||
|
||||
# generate footer
|
||||
footer = """endmodule\n"""
|
||||
|
||||
# aggregate module definitions and remove duplicates
|
||||
module_defs_with_dups = [self.interface.rx_hdl_def()] + [core.hdl_def() for core in self.cores] + [self.interface.tx_hdl_def()]
|
||||
module_defs = []
|
||||
module_defs = [m_def for m_def in module_defs_with_dups if m_def not in module_defs]
|
||||
module_defs = '\n'.join(module_defs)
|
||||
|
||||
# assemble all the parts
|
||||
hdl = header + interface_rx + core_chain + interface_tx + footer
|
||||
hdl += "\n /* ---- Module Definitions ---- */\n"
|
||||
hdl += module_defs
|
||||
|
||||
# default_nettype and timescale directives only at the beginning and end
|
||||
hdl = hdl.replace("`default_nettype none", "")
|
||||
hdl = hdl.replace("`default_nettype wire", "")
|
||||
hdl = hdl.replace("`timescale 1ns/1ps", "")
|
||||
|
||||
hdl = "`default_nettype none\n" + "`timescale 1ns/1ps\n" + hdl + "`default_nettype wire"
|
||||
return hdl
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
`default_nettype none
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module uart_tx(
|
||||
input wire clk,
|
||||
|
|
|
|||
|
|
@ -0,0 +1,4 @@
|
|||
from manta import Manta
|
||||
|
||||
m = Manta('/Users/fischerm/fpga/manta/examples/nexys_a7/single_lut_ram/manta.yaml')
|
||||
print (m.generate_hdl())
|
||||
Loading…
Reference in New Issue