add initialls logic_analyzer core
This commit is contained in:
Fischer Moseley
parent
4540aebf6d
commit
fade794333
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@ -3,7 +3,6 @@ on:
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push:
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branches:
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- main
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- rearch
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permissions:
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contents: write
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jobs:
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13
Makefile
13
Makefile
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@ -8,19 +8,24 @@ lint:
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python3 -m black src/manta/__init__.py
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python3 -m black src/manta/__main__.py
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sim: sim_bit_fifo sim_bridge_rx sim_bridge_tx fifo_tb lut_ram_tb uart_tx_tb
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sim: bit_fifo_tb bridge_rx_tb bridge_tx_tb fifo_tb lut_ram_tb uart_tx_tb
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sim_bit_fifo:
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logic_analyzer_tb:
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iverilog -g2012 -o sim.out test/logic_analyzer_tb.sv src/manta/logic_analyzer.v src/manta/fifo.v src/manta/trigger.v src/manta/xilinx_true_dual_port_read_first_2_clock_ram.v
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vvp sim.out
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rm sim.out
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bit_fifo_tb:
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iverilog -g2012 -o sim.out test/bit_fifo_tb.sv src/manta/bit_fifo.v
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vvp sim.out
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rm sim.out
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sim_bridge_rx:
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bridge_rx_tb:
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iverilog -g2012 -o sim.out test/bridge_rx_tb.sv src/manta/bridge_rx.v
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vvp sim.out
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rm sim.out
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sim_bridge_tx:
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bridge_tx_tb:
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iverilog -g2012 -o sim.out test/bridge_tx_tb.sv src/manta/bridge_tx.v src/manta/uart_tx.v
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vvp sim.out
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rm sim.out
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@ -3,14 +3,14 @@
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module fifo (
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input wire clk,
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input wire rst,
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input wire bram_rst,
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input wire [WIDTH - 1:0] data_in,
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input wire input_ready,
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input wire [WIDTH - 1:0] in,
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input wire in_valid,
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input wire request_output,
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output reg [WIDTH - 1:0] data_out,
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output reg output_valid,
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output reg [WIDTH - 1:0] out,
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input wire out_req,
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output reg out_valid,
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output reg [AW:0] size,
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output reg empty,
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@ -28,28 +28,24 @@ module fifo (
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assign empty_int = (write_pointer[AW] == read_pointer[AW]);
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reg full_or_empty;
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assign full_or_empty = (write_pointer[AW-1:0] == read_pointer[AW-1:0]);
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assign full_or_empty = (write_pointer[AW-1:0] == read_pointer[AW-1:0]);
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assign full = full_or_empty & !empty_int;
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assign empty = full_or_empty & empty_int;
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assign size = write_pointer - read_pointer;
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reg output_valid_pip_0;
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reg output_valid_pip_1;
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reg out_valid_pip_0;
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reg out_valid_pip_1;
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always @(posedge clk) begin
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if (input_ready && ~full)
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if (in_valid && ~full)
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write_pointer <= write_pointer + 1'd1;
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if (request_output && ~empty)
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if (out_req && ~empty) begin
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read_pointer <= read_pointer + 1'd1;
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output_valid_pip_0 <= request_output;
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output_valid_pip_1 <= output_valid_pip_0;
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output_valid <= output_valid_pip_1;
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if (rst) begin
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read_pointer <= 0;
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write_pointer <= 0;
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out_valid_pip_0 <= out_req;
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out_valid_pip_1 <= out_valid_pip_0;
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out_valid <= out_valid_pip_1;
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end
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end
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@ -62,23 +58,23 @@ module fifo (
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// write port
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.clka(clk),
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.rsta(rst),
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.ena(1),
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.rsta(bram_rst),
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.ena(1'b1),
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.addra(write_pointer),
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.dina(data_in),
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.wea(input_ready),
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.regcea(1),
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.dina(in),
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.wea(in_valid),
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.regcea(1'b1),
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.douta(),
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// read port
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.clkb(clk),
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.rstb(rst),
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.enb(1),
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.rstb(bram_rst),
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.enb(1'b1),
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.addrb(read_pointer),
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.dinb(),
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.web(0),
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.regceb(1),
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.doutb(data_out));
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.web(1'b0),
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.regceb(1'b1),
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.doutb(out));
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endmodule
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`default_nettype wire
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@ -0,0 +1,226 @@
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`default_nettype none
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`timescale 1ns/1ps
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module logic_analyzer(
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input wire clk,
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// probes
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input wire larry,
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input wire curly,
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input wire moe,
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input wire [3:0] shemp,
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// input port
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input wire [15:0] addr_i,
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input wire [15:0] wdata_i,
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input wire [15:0] rdata_i,
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input wire rw_i,
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input wire valid_i,
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// output port
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output reg [15:0] addr_o,
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output reg [15:0] wdata_o,
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output reg [15:0] rdata_o,
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output reg rw_o,
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output reg valid_o
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);
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parameter BASE_ADDR = 0;
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parameter SAMPLE_DEPTH = 4096;
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// trigger configuration registers
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// - each probe gets an operation and a compare register
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// - at the end we AND them all together. along with any custom probes the user specs
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reg [3:0] larry_trigger_op;
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reg larry_trigger_arg;
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reg larry_trig;
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trigger #(.INPUT_WIDTH(1)) larry_trigger(
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.clk(clk),
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.probe(larry),
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.op(larry_trigger_op),
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.arg(larry_trigger_arg),
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.trig(larry_trig));
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reg [3:0] curly_trigger_op;
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reg curly_trigger_arg;
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reg curly_trig;
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trigger #(.INPUT_WIDTH(1)) curly_trigger(
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.clk(clk),
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.probe(curly),
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.op(curly_trigger_op),
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.arg(curly_trigger_arg),
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.trig(curly_trig));
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reg [3:0] moe_trigger_op;
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reg moe_trigger_arg;
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reg moe_trig;
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trigger #(.INPUT_WIDTH(1)) moe_trigger(
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.clk(clk),
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.probe(moe),
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.op(moe_trigger_op),
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.arg(moe_trigger_arg),
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.trig(moe_trig));
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reg [3:0] shemp_trigger_op;
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reg [3:0] shemp_trigger_arg;
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reg shemp_trig;
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trigger #(.INPUT_WIDTH(4)) shemp_trigger(
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.clk(clk),
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.probe(shemp),
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.op(shemp_trigger_op),
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.arg(shemp_trigger_arg),
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.trig(shemp_trig));
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reg triggered;
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assign triggered = larry_trig || curly_trig || moe_trig || shemp_trig;
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reg [6:0] concatenated;
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assign concatenated = {larry, curly, moe, shemp};
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// word-wise fifo
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fifo #(.WIDTH(FIFO_WIDTH), .DEPTH(SAMPLE_DEPTH)) wfifo(
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.clk(clk),
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.bram_rst(1'b0),
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.in(concatenated),
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.in_valid(wfifo_in_valid),
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.out(wfifo_out),
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.out_req(wfifo_out_req),
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.out_valid(wfifo_out_valid),
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.size(wfifo_size),
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.empty(),
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.full());
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reg wfifo_in_valid;
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localparam FIFO_WIDTH = 7;
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reg [FIFO_WIDTH-1:0] wfifo_out;
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reg wfifo_out_req;
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reg wfifo_out_valid;
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reg [$clog2(SAMPLE_DEPTH):0] wfifo_size;
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// state machine
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localparam IDLE = 0;
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localparam START = 1;
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localparam MOVE_TO_POSITION = 2;
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localparam IN_POSITION = 3;
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localparam FILLING_BUFFER = 4;
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localparam FILLED = 5;
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reg [3:0] state;
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initial state = IDLE;
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reg signed [15:0] trigger_loc;
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initial trigger_loc = 0;
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reg signed [15:0] present_loc;
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initial present_loc = 0;
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always @(posedge clk) begin
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if(state == IDLE) begin
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present_loc <= (trigger_loc < 0) ? trigger_loc : 0;
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end
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else if(state == MOVE_TO_POSITION) begin
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// if trigger location is negative or zero,
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// then we're already in position
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if(trigger_loc <= 0) state <= IN_POSITION;
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// otherwise we'll need to wait a little,
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// but we'll need to buffer along the way
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else begin
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present_loc <= present_loc + 1;
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// add code to add samples to word FIFO
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wfifo_in_valid <= 1;
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if (present_loc == trigger_loc) state <= IN_POSITION;
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end
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end
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else if(state == IN_POSITION) begin
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// pop stuff out of the word FIFO in addition to pulling it in
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wfifo_in_valid <= 1;
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wfifo_out_req <= 1;
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if(triggered) state <= FILLING_BUFFER;
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end
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else if(state == FILLING_BUFFER) begin
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if(wfifo_size == SAMPLE_DEPTH) state <= FILLED;
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end
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else if(state == FILLED) begin
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// don't automatically go back to IDLE, the host will move
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// the state to MOVE_TO_POSITION
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present_loc <= (trigger_loc < 0) ? trigger_loc : 0;
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end
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end
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// memory servicing
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// - TODO: add support for comparision values > 16 bits,
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// we'll have to concat them somwehere up here
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always @(posedge clk) begin
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addr_o <= addr_i;
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wdata_o <= wdata_i;
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rdata_o <= rdata_i;
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rw_o <= rw_i;
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valid_o <= valid_i;
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// operations to configuration registers
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if( (addr_i >= BASE_ADDR) && (addr_i <= BASE_ADDR + 9) ) begin
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// reads
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if(valid_i && !rw_i) begin
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case (addr_i)
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BASE_ADDR + 0: rdata_o <= state;
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BASE_ADDR + 1: rdata_o <= trigger_loc;
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BASE_ADDR + 2: rdata_o <= larry_trigger_op;
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BASE_ADDR + 3: rdata_o <= larry_trigger_arg;
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BASE_ADDR + 4: rdata_o <= curly_trigger_op;
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BASE_ADDR + 5: rdata_o <= curly_trigger_arg;
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BASE_ADDR + 6: rdata_o <= moe_trigger_op;
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BASE_ADDR + 7: rdata_o <= moe_trigger_arg;
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BASE_ADDR + 8: rdata_o <= shemp_trigger_op;
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BASE_ADDR + 9: rdata_o <= shemp_trigger_arg;
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default: rdata_o <= rdata_i;
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endcase
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end
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// writes
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else if(valid_i && rw_i) begin
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case (addr_i)
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BASE_ADDR + 0: state <= wdata_i;
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BASE_ADDR + 1: trigger_loc <= wdata_i;
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BASE_ADDR + 2: larry_trigger_op <= wdata_i;
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BASE_ADDR + 3: larry_trigger_arg <= wdata_i;
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BASE_ADDR + 4: curly_trigger_op <= wdata_i;
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BASE_ADDR + 5: curly_trigger_arg <= wdata_i;
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BASE_ADDR + 6: moe_trigger_op <= wdata_i;
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BASE_ADDR + 7: moe_trigger_arg <= wdata_i;
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BASE_ADDR + 8: shemp_trigger_op <= wdata_i;
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BASE_ADDR + 9: shemp_trigger_arg <= wdata_i;
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default: wdata_o <= wdata_i;
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endcase
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end
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end
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// operations to BRAM
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else if( (addr_i >= BASE_ADDR + 10) && (addr_i <= BASE_ADDR + 10 + SAMPLE_DEPTH) ) begin
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end
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end
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endmodule
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`default_nettype wire
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@ -0,0 +1,47 @@
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`default_nettype none
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`timescale 1ns/1ps
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module trigger(
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input wire clk,
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input wire [INPUT_WIDTH-1:0] probe,
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input wire [3:0] op,
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input wire [INPUT_WIDTH-1:0] arg,
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output reg trig
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);
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parameter INPUT_WIDTH = 0;
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localparam DISABLE = 0;
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localparam RISING = 1;
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localparam FALLING = 2;
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localparam CHANGING = 3;
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localparam GT = 4;
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localparam LT = 5;
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localparam GEQ = 6;
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localparam LEQ = 7;
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localparam EQ = 8;
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localparam NEQ = 9;
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reg [INPUT_WIDTH-1:0] probe_prev;
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initial probe_prev = probe;
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always @(posedge clk) probe_prev <= probe;
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always @(*) begin
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case (op)
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RISING : trig = (probe > probe_prev);
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FALLING : trig = (probe < probe_prev);
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CHANGING : trig = (probe != probe_prev);
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GT: trig = (probe > arg);
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LT: trig = (probe < arg);
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GEQ: trig = (probe >= arg);
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LEQ: trig = (probe <= arg);
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EQ: trig = (probe == arg);
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NEQ: trig = (probe != arg);
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default: trig = 0;
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endcase
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end
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endmodule
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`default_nettype wire
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@ -0,0 +1,231 @@
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`default_nettype none
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`define CP 10
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`define HCP 5
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module logic_analyzer_tb;
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// boilerplate
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logic clk;
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integer test_num;
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// signal generator
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logic larry;
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logic curly;
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logic moe;
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logic [3:0] shemp;
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// tb -> la bus
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logic [15:0] tb_la_addr;
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logic [15:0] tb_la_wdata;
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logic [15:0] tb_la_rdata;
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logic tb_la_rw;
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logic tb_la_valid;
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// la -> tb bus
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logic [15:0] la_tb_addr;
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logic [15:0] la_tb_wdata;
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logic [15:0] la_tb_rdata;
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logic la_tb_rw;
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logic la_tb_valid;
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logic_analyzer la(
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.clk(clk),
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// probes
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.larry(larry),
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.curly(curly),
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.moe(moe),
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.shemp(shemp),
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// input port
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.addr_i(tb_la_addr),
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.wdata_i(tb_la_wdata),
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.rdata_i(tb_la_rdata),
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.rw_i(tb_la_rw),
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.valid_i(tb_la_valid),
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// output port
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.addr_o(la_tb_addr),
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.wdata_o(la_tb_wdata),
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.rdata_o(la_tb_rdata),
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.rw_o(la_tb_rw),
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.valid_o(la_tb_valid));
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always begin
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#`HCP
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clk = !clk;
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end
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initial begin
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$dumpfile("logic_analyzer_tb.vcd");
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$dumpvars(0, logic_analyzer_tb);
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// setup and reset
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clk = 0;
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test_num = 0;
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tb_la_addr = 0;
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tb_la_rdata = 0;
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tb_la_wdata = 0;
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tb_la_rw = 0;
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tb_la_valid = 0;
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larry = 0;
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curly = 0;
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moe = 0;
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shemp = 0;
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#`HCP
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#(10*`CP);
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/* ==== Test 1 Begin ==== */
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$display("\n=== test 1: read state register ===");
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test_num = 1;
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tb_la_addr = 0;
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tb_la_valid = 1;
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#`CP
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tb_la_valid = 0;
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while (!la_tb_valid) #`CP;
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$display(" -> read 0x%h from state reg (addr 0x0000)", la_tb_rdata);
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#(10*`CP);
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/* ==== Test 1 End ==== */
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|
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|
||||
|
||||
/* ==== Test 2 Begin ==== */
|
||||
$display("\n=== test 2: write to state register and verify ===");
|
||||
test_num = 2;
|
||||
|
||||
// write
|
||||
tb_la_addr = 0;
|
||||
tb_la_valid = 1;
|
||||
tb_la_rw = 1;
|
||||
tb_la_wdata = 5;
|
||||
#`CP
|
||||
tb_la_valid = 0;
|
||||
#`CP
|
||||
$display(" -> wrote 0x0005 to state reg (addr 0x0000)");
|
||||
|
||||
// read
|
||||
tb_la_valid = 1;
|
||||
tb_la_rw = 0;
|
||||
#`CP
|
||||
tb_la_valid = 0;
|
||||
while (!la_tb_valid) #`CP;
|
||||
$display(" -> read 0x%h from state reg (addr 0x0000)", la_tb_rdata);
|
||||
|
||||
|
||||
#(10*`CP);
|
||||
/* ==== Test 2 End ==== */
|
||||
|
||||
|
||||
|
||||
/* ==== Test 3 Begin ==== */
|
||||
$display("\n=== test 3: write to trigger_loc register and verify ===");
|
||||
test_num = 3;
|
||||
|
||||
// write
|
||||
tb_la_addr = 1;
|
||||
tb_la_valid = 1;
|
||||
tb_la_rw = 1;
|
||||
tb_la_wdata = -16'sd69;
|
||||
#`CP
|
||||
tb_la_valid = 0;
|
||||
#`CP
|
||||
$display(" -> wrote -0d69 to trigger_loc reg (addr 0x0001)");
|
||||
|
||||
// read
|
||||
tb_la_valid = 1;
|
||||
tb_la_rw = 0;
|
||||
#`CP
|
||||
tb_la_valid = 0;
|
||||
while (!la_tb_valid) #`CP;
|
||||
$display(" -> read 0d%d from trigger_loc reg (addr 0x0001)", $signed(la_tb_rdata));
|
||||
|
||||
|
||||
#(10*`CP);
|
||||
/* ==== Test 3 End ==== */
|
||||
|
||||
|
||||
|
||||
/* ==== Test 4 Begin ==== */
|
||||
$display("\n=== test 4: configure larry_op for equality and verify ===");
|
||||
test_num = 4;
|
||||
|
||||
// write
|
||||
tb_la_addr = 2;
|
||||
tb_la_valid = 1;
|
||||
tb_la_rw = 1;
|
||||
tb_la_wdata = 8;
|
||||
#`CP
|
||||
tb_la_valid = 0;
|
||||
#`CP
|
||||
$display(" -> wrote 0x0008 to larry_op reg (addr 0x0002)");
|
||||
|
||||
// read
|
||||
tb_la_valid = 1;
|
||||
tb_la_rw = 0;
|
||||
#`CP
|
||||
tb_la_valid = 0;
|
||||
while (!la_tb_valid) #`CP;
|
||||
$display(" -> read 0x%h from larry_op reg (addr 0x0002)", la_tb_rdata);
|
||||
|
||||
|
||||
#(10*`CP);
|
||||
/* ==== Test 4 End ==== */
|
||||
|
||||
|
||||
|
||||
/* ==== Test 5 Begin ==== */
|
||||
$display("\n=== test 5: write 0x0001 to larry_arg register and verify ===");
|
||||
test_num = 5;
|
||||
|
||||
// write
|
||||
tb_la_addr = 3;
|
||||
tb_la_valid = 1;
|
||||
tb_la_rw = 1;
|
||||
tb_la_wdata = 1;
|
||||
#`CP
|
||||
tb_la_valid = 0;
|
||||
#`CP
|
||||
$display(" -> wrote 0x0001 to larry_arg reg (addr 0x0003)");
|
||||
|
||||
// read
|
||||
tb_la_valid = 1;
|
||||
tb_la_rw = 0;
|
||||
#`CP
|
||||
tb_la_valid = 0;
|
||||
while (!la_tb_valid) #`CP;
|
||||
$display(" -> read 0x%h from larry_arg reg (addr 0x0003)", la_tb_rdata);
|
||||
|
||||
|
||||
#(10*`CP);
|
||||
/* ==== Test 5 End ==== */
|
||||
|
||||
|
||||
|
||||
/* ==== Test 6 Begin ==== */
|
||||
$display("\n=== test 6: set larry = 1, verify core does not trigger ===");
|
||||
test_num = 6;
|
||||
|
||||
larry = 1;
|
||||
$display(" -> set larry = 1");
|
||||
|
||||
// read
|
||||
$display(" -> la core is in state 0x%h", la.state);
|
||||
#`CP
|
||||
$display(" -> la core is in state 0x%h", la.state);
|
||||
|
||||
|
||||
#(10*`CP);
|
||||
/* ==== Test 6 End ==== */
|
||||
|
||||
$finish();
|
||||
end
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
Loading…
Reference in New Issue