refactor to separate verilog and python
This commit is contained in:
Fischer Moseley
parent
621ca48ad3
commit
20957e5ba7
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@ -5,10 +5,28 @@ jobs:
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runs-on: ubuntu-latest
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steps:
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- uses: actions/checkout@v3
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- name: install yosys
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- name: Install Manta from Source
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run: |
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pip install setuptools --upgrade
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# omitting the following commmand causes the version of setuptools
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# used by python to get confused, and it doesn't detect the name
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# or version of the package from pyproject.toml - so the following
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# workaround is used:
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# https://github.com/pypa/setuptools/issues/3269#issuecomment-1254507377
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export DEB_PYTHON_INSTALL_LAYOUT=deb_system
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python3 -m pip install .
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- name: Install Icestorm Tools
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run: |
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wget --no-verbose https://github.com/YosysHQ/oss-cad-suite-build/releases/download/2023-02-23/oss-cad-suite-linux-x64-20230223.tgz
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tar -xzf oss-cad-suite-linux-x64-20230223.tgz
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tar -xzf oss-cad-suite-linux-x64-20230223.tgz
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export PATH="$(pwd)/oss-cad-suite/bin/:$PATH"
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cd examples/icestick/counter
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./build.sh
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- name: Build io_core
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run: make icestick_io_core
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- name: Build lut_ram
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run: make icestick_lut_ram
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@ -26,13 +26,11 @@ jobs:
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python3 -m pip install .
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- name: Generate Core
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run: manta gen examples/nexys_a7/counter/manta.yaml examples/nexys_a7/counter/src/debug.sv
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- name: Build io_core
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run: make nexys_a7_io_core
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- name: Build Verilog
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working-directory: examples/nexys_a7/counter
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run: mkdir obj && python3 lab-bc.py
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- name: Build logic_analyzer
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run: make nexys_a7_logic_analyzer
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- name: Print build.log
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working-directory: examples/nexys_a7/counter
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run: cat obj/build.log
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- name: Build lut_ram
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run: make nexys_a7_lut_ram
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@ -5,6 +5,94 @@ from datetime import datetime
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version = "0.0.0"
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class VerilogManipulator:
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def __init__(self, filepath=None):
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if filepath is not None:
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self.hdl = pkgutil.get_data(__name__, filepath).decode()
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else:
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self.hdl = None
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def sub(self, replace, find):
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# sometimes we have integer inputs, want to accomodate
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if isinstance(replace, str):
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replace_str = replace
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elif isinstance(replace, int):
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replace_str = str(replace)
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else:
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raise ValueError("Only string and integer arguments supported.")
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# if the string being subbed in isn't multiline, just
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# find-and-replace like normal:
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if "\n" not in replace_str:
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self.hdl = self.hdl.replace(find, replace_str)
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# if the string being substituted in is multiline,
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# make sure the replace text gets put at the same
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# indentation level by adding whitespace to left
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# of the line.
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else:
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for line in self.hdl.split("\n"):
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if find in line:
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# get whitespace that's on the left side of the line
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whitespace = line.rstrip().replace(line.lstrip(), "")
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# add it to every line, except the first
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replace_as_lines = replace_str.split("\n")
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replace_with_whitespace = f"\n{whitespace}".join(replace_as_lines)
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# replace the first occurance in the HDL with it
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self.hdl = self.hdl.replace(find, replace_with_whitespace, 1)
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def get_hdl(self):
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return self.hdl
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def net_dec(self, nets, net_type, trailing_comma = False):
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"""Takes a dictonary of nets in the format {probe: width}, and generates
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the net declarations that would go in a Verilog module definition.
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For example, calling net_dec({foo : 1, bar : 4}, "input wire") would produce:
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input wire foo,
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input [3:0] wire bar
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Which you'd then slap into your module declaration, along with all the other
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inputs and outputs the module needs."""
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dec = []
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for name, width in nets.items():
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if width == 1:
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dec.append(f"{net_type} {name}")
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else:
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dec.append(f"{net_type} [{width-1}:0] {name}")
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dec = ",\n".join(dec)
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dec = dec + "," if trailing_comma else dec
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return dec
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def net_conn(self, nets, trailing_comma = False):
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"""Takes a dictionary of nets in the format {probe: width}, and generates
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the net connections that would go in the Verilog module instantiation.
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For example, calling net_conn({foo: 1, bar: 4}) would produce:
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.foo(foo),
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.bar(bar)
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Which you'd then slap into your module instantiation, along with all the other
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module inputs and outputs that get connected elsewhere."""
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conn = [f".{name}({name})" for name in nets]
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conn = ",\n".join(conn)
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conn = conn + "," if trailing_comma else conn
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return conn
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class UARTInterface:
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def __init__(self, config):
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# Obtain port. Try to automatically detect port if "auto" is specified
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@ -112,63 +200,24 @@ class UARTInterface:
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return ["input wire rx", "output reg tx"]
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def rx_hdl_def(self):
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uart_rx_def = pkgutil.get_data(__name__, "rx_uart.v").decode()
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bridge_rx_def = pkgutil.get_data(__name__, "bridge_rx.v").decode()
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uart_rx_def = VerilogManipulator("rx_uart.v").get_hdl()
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bridge_rx_def = VerilogManipulator("bridge_rx.v").get_hdl()
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return uart_rx_def + '\n' + bridge_rx_def
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def tx_hdl_def(self):
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uart_tx_def = pkgutil.get_data(__name__, "uart_tx.v").decode()
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bridge_tx_def = pkgutil.get_data(__name__, "bridge_tx.v").decode()
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uart_tx_def = VerilogManipulator("uart_tx.v").get_hdl()
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bridge_tx_def = VerilogManipulator("bridge_tx.v").get_hdl()
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return bridge_tx_def + '\n' + uart_tx_def
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def rx_hdl_inst(self):
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return f"""
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rx_uart #(.CLOCKS_PER_BAUD({self.clocks_per_baud})) urx (
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.i_clk(clk),
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.i_uart_rx(rx),
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.o_wr(urx_brx_axiv),
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.o_data(urx_brx_axid));
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logic [7:0] urx_brx_axid;
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logic urx_brx_axiv;
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bridge_rx brx (
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.clk(clk),
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.rx_data(urx_brx_axid),
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.rx_valid(urx_brx_axiv),
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.addr_o(),
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.wdata_o(),
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.rw_o(),
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.valid_o());
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"""
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rx = VerilogManipulator("uart_rx_bridge_rx_inst_templ.v")
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rx.sub(self.clocks_per_baud, "/* CLOCKS_PER_BAUD */")
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return rx.get_hdl()
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def tx_hdl_inst(self):
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return f"""
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bridge_tx btx (
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.clk(clk),
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.rdata_i(),
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.rw_i(),
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.valid_i(),
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.ready_i(utx_btx_ready),
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.data_o(btx_utx_data),
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.valid_o(btx_utx_valid));
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logic utx_btx_ready;
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logic btx_utx_valid;
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logic [7:0] btx_utx_data;
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uart_tx #(.CLOCKS_PER_BAUD({self.clocks_per_baud})) utx (
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.clk(clk),
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.data(btx_utx_data),
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.valid(btx_utx_valid),
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.ready(utx_btx_ready),
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.tx(tx));\n"""
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tx = VerilogManipulator("uart_tx_bridge_tx_inst_templ.v")
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tx.sub(self.clocks_per_baud, "/* CLOCKS_PER_BAUD */")
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return tx.get_hdl()
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class IOCoreProbe:
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def __init__(self, name, width, direction, base_addr, interface):
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@ -241,120 +290,62 @@ class IOCore:
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def hdl_inst(self):
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# TODO: make this a string comprehension
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inst_ports = [f".{probe.name}({probe.name}),\n " for probe in self.probes]
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inst_ports = "".join(inst_ports)
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inst_ports = inst_ports.rstrip()
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inst = VerilogManipulator("io_core_inst_tmpl.v")
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inst.sub(self.name, "/* MODULE_NAME */")
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inst.sub(self.name + "_inst", "/* INST_NAME */")
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return f"""
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{self.name} {self.name}_inst(
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.clk(clk),
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probes = {probe.name:probe.width for probe in self.probes}
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// ports
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{inst_ports}
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inst_ports = inst.net_conn(probes, trailing_comma=True)
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inst.sub(inst_ports, "/* INST_PORTS */")
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// input port
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.addr_i(),
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.wdata_i(),
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.rdata_i(),
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.rw_i(),
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.valid_i(),
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return inst.get_hdl()
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// output port
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.addr_o(),
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.wdata_o(),
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.rdata_o(),
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.rw_o(),
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.valid_o()
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);
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"""
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def hdl_def(self):
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io_core = VerilogManipulator("io_core_def_tmpl.v")
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io_core.sub(self.name, "/* MODULE_NAME */")
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io_core.sub(self.max_addr, "/* MAX_ADDR */")
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# generate declaration
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top_level_ports = ',\n '.join(self.hdl_top_level_ports())
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top_level_ports = ',\n'.join(self.hdl_top_level_ports())
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top_level_ports += ','
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declaration = f"""
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module {self.name} (
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input wire clk,
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// ports
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{top_level_ports}
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// input port
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input wire [15:0] addr_i,
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input wire [15:0] wdata_i,
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input wire [15:0] rdata_i,
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input wire rw_i,
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input wire valid_i,
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// output port
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output reg [15:0] addr_o,
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output reg [15:0] wdata_o,
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output reg [15:0] rdata_o,
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output reg rw_o,
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output reg valid_o
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);
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"""
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io_core.sub(top_level_ports, "/* TOP_LEVEL_PORTS */")
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# generate memory handling
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read_case_statement_body = ""
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write_case_statement_body = ""
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rcsb = "" # read case statement body
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wcsb = "" # write case statement body
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for probe in self.probes:
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# add to read block
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if probe.width == 16:
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read_case_statement_body += f"\t\t\t\t\t{probe.base_addr}: rdata_o <= {probe.name};\n"
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rcsb += f"{probe.base_addr}: rdata_o <= {probe.name};\n"
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else:
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read_case_statement_body += f"\t\t\t\t\t{probe.base_addr}: rdata_o <= {{{16-probe.width}'b0, {probe.name}}};\n"
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rcsb += f"{probe.base_addr}: rdata_o <= {{{16-probe.width}'b0, {probe.name}}};\n"
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# if output, add to write block
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if probe.direction == "output":
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if probe.width == 1:
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write_case_statement_body += f"\t\t\t\t\t{probe.base_addr}: {probe.name} <= wdata_i[0];\n"
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wcsb += f"{probe.base_addr}: {probe.name} <= wdata_i[0];\n"
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elif probe.width == 16:
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write_case_statement_body += f"\t\t\t\t\t{probe.base_addr}: {probe.name} <= wdata_i;\n"
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wcsb += f"{probe.base_addr}: {probe.name} <= wdata_i;\n"
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else:
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write_case_statement_body += f"\t\t\t\t\t{probe.base_addr}: {probe.name} <= wdata_i[{probe.width-1}:0];\n"
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wcsb += f"{probe.base_addr}: {probe.name} <= wdata_i[{probe.width-1}:0];\n"
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# remove trailing newline
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read_case_statement_body = read_case_statement_body.rstrip()
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write_case_statement_body = write_case_statement_body.rstrip()
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rcsb = rcsb.rstrip()
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wcsb = wcsb.rstrip()
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memory_handler_hdl = f"""
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parameter BASE_ADDR = 0;
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always @(posedge clk) begin
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addr_o <= addr_i;
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wdata_o <= wdata_i;
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rdata_o <= rdata_i;
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rw_o <= rw_i;
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valid_o <= valid_i;
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rdata_o <= rdata_i;
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io_core.sub(rcsb, "/* READ_CASE_STATEMENT_BODY */")
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io_core.sub(wcsb, "/* WRITE_CASE_STATEMENT_BODY */")
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return io_core.get_hdl()
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// check if address is valid
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if( (valid_i) && (addr_i >= BASE_ADDR) && (addr_i <= BASE_ADDR + {self.max_addr})) begin
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if(!rw_i) begin // reads
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case (addr_i)
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{read_case_statement_body}
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endcase
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end
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else begin // writes
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case (addr_i)
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{write_case_statement_body}
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endcase
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end
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end
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end
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"""
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hdl = declaration + memory_handler_hdl + "endmodule"
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return hdl
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def hdl_top_level_ports(self):
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ports = []
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@ -379,31 +370,17 @@ class LUTRAMCore:
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self.max_addr = self.base_addr + self.size - 1
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def hdl_inst(self):
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hdl = f"""
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lut_ram #(.DEPTH({self.size})) {self.name} (
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.clk(clk),
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.addr_i(),
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.wdata_i(),
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.rdata_i(),
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.rw_i(),
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.valid_i(),
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.addr_o(),
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.wdata_o(),
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.rdata_o(),
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.rw_o(),
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.valid_o());\n"""
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return hdl
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inst = VerilogManipulator("lut_ram_inst_tmpl.v")
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inst.sub(self.size, "/* DEPTH */")
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inst.sub(self.name, "/* INST_NAME */")
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return inst.get_hdl()
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def hdl_def(self):
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hdl = pkgutil.get_data(__name__, "lut_ram.v").decode()
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return hdl
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return VerilogManipulator("lut_ram.v").get_hdl()
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def hdl_top_level_ports(self):
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# no top_level connections since this core just lives on the bus
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return []
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return ""
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def read(self, addr):
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return self.interface.read_register(addr + self.base_addr)
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@ -448,83 +425,59 @@ class LogicAnalyzerCore:
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self.max_addr = self.sample_mem_base_addr + self.sample_depth
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def hdl_inst(self):
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ports = []
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la_inst = VerilogManipulator("logic_analyzer_inst_tmpl.v")
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ports = [f".{name}({name})," for name in self.probes.keys()]
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ports = "\n\t\t".join(ports)
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# add module name to instantiation
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la_inst.sub(self.name, "/* INST_NAME */")
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hdl = f"""
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logic_analyzer {self.name} (
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.clk(clk),
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# add net connections to instantiation
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conns = la_inst.net_conn(self.probes, trailing_comma=True)
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la_inst.sub(conns, "/* NET_CONNS */")
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return la_inst.get_hdl()
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.addr_i(),
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.wdata_i(),
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.rdata_i(),
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.rw_i(),
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.valid_i(),
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{ports}
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.addr_o(),
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.wdata_o(),
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.rdata_o(),
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.rw_o(),
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.valid_o());\n"""
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return hdl
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def generate_trigger_block(self):
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trigger_block_hdl = pkgutil.get_data(__name__, "trigger_block_template.v").decode()
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def gen_trigger_block_def(self):
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trigger_block = VerilogManipulator("trigger_block_template.v")
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# add probe ports to module declaration
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# - these are the ports that belong to the logic analyzer, but
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# need to be included in the trigger_block module declaration
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probe_ports = []
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for name, width in self.probes.items():
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if width == 1:
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probe_ports.append(f"input wire {name}")
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else:
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probe_ports.append(f"input wire [{width-1}:0] {name}")
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# these ports belong to the logic analyzer, but
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# need to be included in the trigger_block module declaration
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probe_ports = trigger_block.net_dec(self.probes, "input wire", trailing_comma=True)
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||||
trigger_block.sub(probe_ports, "/* PROBE_PORTS */")
|
||||
|
||||
probe_ports = ",\n\t".join(probe_ports)
|
||||
probe_ports = probe_ports + ","
|
||||
trigger_block_hdl = trigger_block_hdl.replace("// @PROBE_PORTS", probe_ports)
|
||||
|
||||
# add trigger cores to module definition
|
||||
# - these are instances of the trigger module, of which one gets wired
|
||||
# into each probe
|
||||
# these are instances of the trigger module, of which one gets wired
|
||||
# into each probe
|
||||
trigger_module_insts = []
|
||||
for name, width in self.probes.items():
|
||||
trigger_module_inst = f"reg [3:0] {name}_trigger_op = 0;\n\t"
|
||||
trig_inst = VerilogManipulator("trigger_block_inst_tmpl.v")
|
||||
trig_inst.sub(width, "/* INPUT_WIDTH */")
|
||||
trig_inst.sub(f"{name}_trigger", "/* NAME */")
|
||||
|
||||
trig_inst.sub(f"reg [3:0] {name}_op = 0;", "/* OP_DEC */")
|
||||
trig_inst.sub(f"reg {name}_trig;", "/* TRIG_DEC */")
|
||||
|
||||
if width == 1:
|
||||
trigger_module_inst += f"reg {name}_trigger_arg = 0;\n\t"
|
||||
trig_inst.sub(f"reg {name}_arg = 0;", "/* ARG_DEC */")
|
||||
|
||||
else:
|
||||
trigger_module_inst += f"reg [{width-1}:0] {name}_trigger_arg = 0;\n\t"
|
||||
trig_inst.sub(f"reg [{width-1}:0] {name}_arg = 0;", "/* ARG_DEC */")
|
||||
|
||||
trigger_module_inst += f"reg {name}_trig;\n\t"
|
||||
trigger_module_inst += f"""
|
||||
trigger #(.INPUT_WIDTH({width})) {name}_trigger (
|
||||
.clk(clk),
|
||||
trig_inst.sub(name, "/* PROBE */")
|
||||
trig_inst.sub(f"{name}_op", "/* OP */")
|
||||
trig_inst.sub(f"{name}_arg", "/* ARG */")
|
||||
trig_inst.sub(f"{name}_trig", "/* TRIG */")
|
||||
|
||||
.probe({name}),
|
||||
.op({name}_trigger_op),
|
||||
.arg({name}_trigger_arg),
|
||||
.trig({name}_trig)
|
||||
);
|
||||
"""
|
||||
trigger_module_insts.append(trigger_module_inst)
|
||||
trigger_module_insts.append(trig_inst.get_hdl())
|
||||
|
||||
trigger_module_insts = "".join(trigger_module_insts)
|
||||
trigger_module_insts = trigger_module_insts.rstrip()
|
||||
trigger_block_hdl = trigger_block_hdl.replace("// @TRIGGER_MODULE_INSTS", trigger_module_insts)
|
||||
trigger_module_insts = "\n".join(trigger_module_insts)
|
||||
trigger_block.sub(trigger_module_insts, "/* TRIGGER_MODULE_INSTS */")
|
||||
|
||||
# add combined individual triggers
|
||||
combined_individual_triggers = [f"{name}_trig" for name in self.probes]
|
||||
combined_individual_triggers = " || ".join(combined_individual_triggers)
|
||||
combined_individual_triggers = f"assign trig = {combined_individual_triggers};"
|
||||
trigger_block_hdl = trigger_block_hdl.replace("// @COMBINE_INDIV_TRIGGERS", combined_individual_triggers)
|
||||
cit = [f"{name}_trig" for name in self.probes]
|
||||
cit = " || ".join(cit)
|
||||
cit = f"assign trig = {cit};"
|
||||
trigger_block.sub(cit, " /* COMBINE_INDIV_TRIGGERS */")
|
||||
|
||||
# add read and write block case statement bodies
|
||||
rcsb = "" # read case statement body
|
||||
|
|
@ -532,38 +485,30 @@ class LogicAnalyzerCore:
|
|||
addr = 0
|
||||
for i, name in enumerate(self.probes):
|
||||
addr = 2 * i
|
||||
rcsb += f"\t\t\t\t\tBASE_ADDR + {addr}: rdata_o <= {name}_trigger_op;\n"
|
||||
wcsb += f"\t\t\t\t\tBASE_ADDR + {addr}: {name}_trigger_op <= wdata_i;\n"
|
||||
rcsb += f"BASE_ADDR + {addr}: rdata_o <= {name}_op;\n"
|
||||
wcsb += f"BASE_ADDR + {addr}: {name}_op <= wdata_i;\n"
|
||||
|
||||
addr = (2 * i) + 1
|
||||
rcsb += f"\t\t\t\t\tBASE_ADDR + {addr}: rdata_o <= {name}_trigger_arg;\n"
|
||||
wcsb += f"\t\t\t\t\tBASE_ADDR + {addr}: {name}_trigger_arg <= wdata_i;\n"
|
||||
rcsb += f"BASE_ADDR + {addr}: rdata_o <= {name}_arg;\n"
|
||||
wcsb += f"BASE_ADDR + {addr}: {name}_arg <= wdata_i;\n"
|
||||
|
||||
rcsb = rcsb.strip()
|
||||
wcsb = wcsb.strip()
|
||||
|
||||
trigger_block_hdl = trigger_block_hdl.replace("// @READ_CASE_STATEMENT_BODY", rcsb)
|
||||
trigger_block_hdl = trigger_block_hdl.replace("// @WRITE_CASE_STATEMENT_BODY", wcsb)
|
||||
trigger_block_hdl = trigger_block_hdl.replace("// @MAX_ADDR", str(addr))
|
||||
return trigger_block_hdl
|
||||
trigger_block.sub(rcsb, "/* READ_CASE_STATEMENT_BODY */")
|
||||
trigger_block.sub(wcsb, "/* WRITE_CASE_STATEMENT_BODY */")
|
||||
trigger_block.sub(addr, "/* MAX_ADDR */")
|
||||
|
||||
def generate_sample_mem(self):
|
||||
sample_mem_hdl = pkgutil.get_data(__name__, "sample_mem_template.v").decode()
|
||||
return trigger_block.get_hdl()
|
||||
|
||||
def gen_sample_mem_def(self):
|
||||
sample_mem = VerilogManipulator("sample_mem_tmpl.v")
|
||||
|
||||
# add probe ports to module declaration
|
||||
# - these are the ports that belong to the logic analyzer, but
|
||||
# need to be included in the trigger_block module declaration
|
||||
probe_ports = []
|
||||
for name, width in self.probes.items():
|
||||
if width == 1:
|
||||
probe_ports.append(f"input wire {name}")
|
||||
else:
|
||||
probe_ports.append(f"input wire [{width-1}:0] {name}")
|
||||
|
||||
probe_ports = ",\n\t".join(probe_ports)
|
||||
probe_ports = probe_ports + ","
|
||||
sample_mem_hdl = sample_mem_hdl.replace("/* PROBE_PORTS */", probe_ports)
|
||||
|
||||
probe_ports = sample_mem.net_dec(self.probes, "input wire", trailing_comma=True)
|
||||
sample_mem.sub(probe_ports, "/* PROBE_PORTS */")
|
||||
|
||||
# concatenate probes to BRAM input
|
||||
total_probe_width = sum([width for name, width in self.probes.items()])
|
||||
|
|
@ -576,76 +521,54 @@ class LogicAnalyzerCore:
|
|||
concat = ", ".join([name for name in self.probes])
|
||||
concat = f"{{{zero_pad_width}'b0, {concat}}}"
|
||||
|
||||
sample_mem_hdl = sample_mem_hdl.replace("/* CONCAT */", concat)
|
||||
sample_mem.sub(concat, "/* CONCAT */")
|
||||
return sample_mem.get_hdl()
|
||||
|
||||
return sample_mem_hdl
|
||||
|
||||
def generate_logic_analyzer(self):
|
||||
logic_analyzer_hdl = pkgutil.get_data(__name__, "logic_analyzer_template.v").decode()
|
||||
def gen_logic_analyzer_def(self):
|
||||
la = VerilogManipulator("logic_analyzer_tmpl.v")
|
||||
|
||||
# add top level probe ports to module declaration
|
||||
# - these are the ports that belong to the logic analyzer, but
|
||||
# need to be included in the trigger_block module declaration
|
||||
|
||||
tlpp = [] # top level probe ports
|
||||
for name, width in self.probes.items():
|
||||
if width == 1:
|
||||
tlpp.append(f"input wire {name}")
|
||||
else:
|
||||
tlpp.append(f"input wire [{width-1}:0] {name}")
|
||||
|
||||
tlpp = ",\n\t".join(tlpp)
|
||||
tlpp = tlpp + ","
|
||||
logic_analyzer_hdl = logic_analyzer_hdl.replace("/* TOP_LEVEL_PROBE_PORTS */", tlpp)
|
||||
ports = la.net_dec(self.probes, "input wire", trailing_comma=True)
|
||||
la.sub(ports, "/* TOP_LEVEL_PROBE_PORTS */")
|
||||
|
||||
# assign base addresses to the FSM, trigger block, and sample mem
|
||||
logic_analyzer_hdl = logic_analyzer_hdl.replace("/* FSM_BASE_ADDR */", str(self.fsm_base_addr))
|
||||
logic_analyzer_hdl = logic_analyzer_hdl.replace("/* TRIGGER_BLOCK_BASE_ADDR */", str(self.trigger_block_base_addr))
|
||||
logic_analyzer_hdl = logic_analyzer_hdl.replace("/* SAMPLE_MEM_BASE_ADDR */", str(self.sample_mem_base_addr))
|
||||
la.sub(self.fsm_base_addr, "/* FSM_BASE_ADDR */")
|
||||
la.sub(self.trigger_block_base_addr, "/* TRIGGER_BLOCK_BASE_ADDR */")
|
||||
la.sub(self.sample_mem_base_addr, "/* SAMPLE_MEM_BASE_ADDR */")
|
||||
|
||||
# set sample depth
|
||||
logic_analyzer_hdl = logic_analyzer_hdl.replace("/* SAMPLE_DEPTH */", str(self.sample_depth))
|
||||
la.sub(self.sample_depth, "/* SAMPLE_DEPTH */")
|
||||
|
||||
# set probe ports for the trigger block and sample mem
|
||||
pp = [] # probe ports
|
||||
pp = [f".{name}({name})" for name in self.probes]
|
||||
pp = ",\n\t\t".join(pp)
|
||||
pp = pp + ","
|
||||
logic_analyzer_hdl = logic_analyzer_hdl.replace("/* TRIGGER_BLOCK_PROBE_PORTS */", pp)
|
||||
logic_analyzer_hdl = logic_analyzer_hdl.replace("/* SAMPLE_MEM_PROBE_PORTS */", pp)
|
||||
|
||||
return logic_analyzer_hdl
|
||||
probe_ports = la.net_conn(self.probes, trailing_comma=True)
|
||||
la.sub(probe_ports, "/* TRIGGER_BLOCK_PROBE_PORTS */")
|
||||
la.sub(probe_ports, "/* SAMPLE_MEM_PROBE_PORTS */")
|
||||
|
||||
return la.get_hdl()
|
||||
|
||||
def hdl_def(self):
|
||||
# Return an autogenerated verilog module definition for the core.
|
||||
# load source files=
|
||||
la_fsm_hdl = pkgutil.get_data(__name__, "la_fsm.v").decode()
|
||||
dual_port_bram_hdl = pkgutil.get_data(__name__, "dual_port_bram.v").decode()
|
||||
trigger_hdl = pkgutil.get_data(__name__, "trigger.v").decode()
|
||||
# load source files
|
||||
la_fsm = VerilogManipulator("la_fsm.v").get_hdl()
|
||||
dual_port_bram = VerilogManipulator("dual_port_bram.v").get_hdl()
|
||||
trigger = VerilogManipulator("trigger.v").get_hdl()
|
||||
trigger_block = self.gen_trigger_block_def()
|
||||
sample_mem = self.gen_sample_mem_def()
|
||||
logic_analyzer = self.gen_logic_analyzer_def()
|
||||
|
||||
# generate trigger block
|
||||
trigger_block_hdl = self.generate_trigger_block()
|
||||
|
||||
# generate sample memory
|
||||
sample_mem_hdl = self.generate_sample_mem()
|
||||
|
||||
# generate logic analyzer
|
||||
logic_analyzer_hdl = self.generate_logic_analyzer()
|
||||
|
||||
return logic_analyzer_hdl + la_fsm_hdl + sample_mem_hdl + dual_port_bram_hdl + trigger_block_hdl + trigger_hdl
|
||||
return logic_analyzer + la_fsm + sample_mem + dual_port_bram + trigger_block + trigger
|
||||
|
||||
def hdl_top_level_ports(self):
|
||||
# this should return the probes that we want to connect to top-level, but as a list of verilog ports
|
||||
|
||||
# the probes that we want as ports on the top-level manta module
|
||||
ports = []
|
||||
for name, width in self.probes.items():
|
||||
if width == 1:
|
||||
ports.append(f"input wire {name}")
|
||||
|
||||
else:
|
||||
ports.append(f"input wire [{width-1}:0] {name}")
|
||||
|
||||
return ports
|
||||
#return VerilogManipulator().net_dec(self.probes, "input wire")
|
||||
|
||||
def run(self):
|
||||
pass
|
||||
|
|
@ -780,7 +703,7 @@ class Manta:
|
|||
|
||||
return config
|
||||
|
||||
def generate_connections(self):
|
||||
def gen_connections(self):
|
||||
# generates hdl for registers that connect two modules together
|
||||
|
||||
# make pairwise cores
|
||||
|
|
@ -800,7 +723,7 @@ class Manta:
|
|||
|
||||
return conns
|
||||
|
||||
def generate_instances(self):
|
||||
def gen_instances(self):
|
||||
# generates hdl for modules that need to be connected together
|
||||
|
||||
insts = []
|
||||
|
|
@ -841,9 +764,9 @@ class Manta:
|
|||
|
||||
return insts
|
||||
|
||||
def generate_core_chain(self):
|
||||
insts = self.generate_instances()
|
||||
conns = self.generate_connections()
|
||||
def gen_core_chain(self):
|
||||
insts = self.gen_instances()
|
||||
conns = self.gen_connections()
|
||||
core_chain = []
|
||||
for i, inst in enumerate(insts):
|
||||
core_chain.append(inst)
|
||||
|
|
@ -853,7 +776,7 @@ class Manta:
|
|||
|
||||
return '\n'.join(core_chain)
|
||||
|
||||
def generate_header(self):
|
||||
def gen_header(self):
|
||||
# generate header
|
||||
user = os.environ.get("USER", os.environ.get("USERNAME"))
|
||||
timestamp = datetime.now().strftime("%d %b %Y at %H:%M:%S")
|
||||
|
|
@ -869,7 +792,7 @@ Provided under a GNU GPLv3 license. Go wild.
|
|||
"""
|
||||
return header
|
||||
|
||||
def generate_ex_inst(self):
|
||||
def gen_example_inst(self):
|
||||
# this is a C-style block comment that contains an instantiation
|
||||
# of the configured manta instance - the idea is that a user
|
||||
# can copy-paste that into their design instead of trying to spot
|
||||
|
|
@ -918,7 +841,7 @@ manta manta_inst (
|
|||
*/
|
||||
"""
|
||||
|
||||
def generate_declaration(self):
|
||||
def gen_declaration(self):
|
||||
# get all the top level connections for each module.
|
||||
|
||||
interface_ports = self.interface.hdl_top_level_ports()
|
||||
|
|
@ -947,7 +870,7 @@ module manta (
|
|||
{ports});
|
||||
"""
|
||||
|
||||
def generate_interface_rx(self):
|
||||
def gen_interface_rx(self):
|
||||
# instantiate interface_rx, substitute in register names
|
||||
interface_rx_inst = self.interface.rx_hdl_inst()
|
||||
|
||||
|
|
@ -965,7 +888,7 @@ module manta (
|
|||
|
||||
return interface_rx_inst + interface_rx_conn
|
||||
|
||||
def generate_interface_tx(self):
|
||||
def gen_interface_tx(self):
|
||||
|
||||
# connect core_chain to interface_tx
|
||||
interface_tx_conn = f"""
|
||||
|
|
@ -983,45 +906,28 @@ module manta (
|
|||
|
||||
return interface_tx_conn + interface_tx_inst
|
||||
|
||||
def generate_footer(self):
|
||||
def gen_footer(self):
|
||||
return """endmodule\n"""
|
||||
|
||||
def generate_module_defs(self):
|
||||
def gen_module_defs(self):
|
||||
# aggregate module definitions and remove duplicates
|
||||
module_defs_with_dups = [self.interface.rx_hdl_def()] + [core.hdl_def() for core in self.cores] + [self.interface.tx_hdl_def()]
|
||||
module_defs = []
|
||||
module_defs = [m_def for m_def in module_defs_with_dups if m_def not in module_defs]
|
||||
return '\n'.join(module_defs)
|
||||
|
||||
|
||||
|
||||
def generate_hdl(self, output_filepath):
|
||||
# generate header
|
||||
header = self.generate_header()
|
||||
|
||||
# generate example instantiation
|
||||
ex_inst = self.generate_ex_inst()
|
||||
|
||||
# generate module declaration
|
||||
declar = self.generate_declaration()
|
||||
|
||||
# generate interface_rx
|
||||
interface_rx = self.generate_interface_rx()
|
||||
|
||||
# generate core chain
|
||||
core_chain = self.generate_core_chain()
|
||||
|
||||
# generate interface_tx
|
||||
interface_tx = self.generate_interface_tx()
|
||||
|
||||
# generate footer
|
||||
footer = self.generate_footer()
|
||||
|
||||
# generate module definitions
|
||||
module_defs = self.generate_module_defs()
|
||||
header = self.gen_header()
|
||||
ex_inst = self.gen_example_inst()
|
||||
declaration = self.gen_declaration() + "\n"
|
||||
interface_rx = self.gen_interface_rx()
|
||||
core_chain = self.gen_core_chain()
|
||||
interface_tx = self.gen_interface_tx()
|
||||
footer = self.gen_footer()
|
||||
module_defs = self.gen_module_defs()
|
||||
|
||||
# assemble all the parts
|
||||
hdl = header + ex_inst + declar + interface_rx + core_chain + interface_tx + footer
|
||||
hdl = header + ex_inst + declaration + interface_rx + core_chain + interface_tx + footer
|
||||
hdl += "\n /* ---- Module Definitions ---- */\n"
|
||||
hdl += module_defs
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,51 @@
|
|||
module /* MODULE_NAME */ (
|
||||
input wire clk,
|
||||
|
||||
// ports
|
||||
/* TOP_LEVEL_PORTS */
|
||||
|
||||
// input port
|
||||
input wire [15:0] addr_i,
|
||||
input wire [15:0] wdata_i,
|
||||
input wire [15:0] rdata_i,
|
||||
input wire rw_i,
|
||||
input wire valid_i,
|
||||
|
||||
// output port
|
||||
output reg [15:0] addr_o,
|
||||
output reg [15:0] wdata_o,
|
||||
output reg [15:0] rdata_o,
|
||||
output reg rw_o,
|
||||
output reg valid_o
|
||||
);
|
||||
|
||||
parameter BASE_ADDR = 0;
|
||||
always @(posedge clk) begin
|
||||
addr_o <= addr_i;
|
||||
wdata_o <= wdata_i;
|
||||
rdata_o <= rdata_i;
|
||||
rw_o <= rw_i;
|
||||
valid_o <= valid_i;
|
||||
rdata_o <= rdata_i;
|
||||
|
||||
|
||||
// check if address is valid
|
||||
if( (valid_i) && (addr_i >= BASE_ADDR) && (addr_i <= BASE_ADDR + /* MAX_ADDR */)) begin
|
||||
|
||||
// reads
|
||||
if(!rw_i) begin
|
||||
case (addr_i)
|
||||
/* READ_CASE_STATEMENT_BODY */
|
||||
endcase
|
||||
end
|
||||
|
||||
// writes
|
||||
else begin
|
||||
case (addr_i)
|
||||
/* WRITE_CASE_STATEMENT_BODY */
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* MODULE_NAME */ /* INST_NAME */ (
|
||||
.clk(clk),
|
||||
|
||||
// ports
|
||||
/* INST_PORTS */
|
||||
|
||||
// input port
|
||||
.addr_i(),
|
||||
.wdata_i(),
|
||||
.rdata_i(),
|
||||
.rw_i(),
|
||||
.valid_i(),
|
||||
|
||||
// output port
|
||||
.addr_o(),
|
||||
.wdata_o(),
|
||||
.rdata_o(),
|
||||
.rw_o(),
|
||||
.valid_o()
|
||||
);
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
logic_analyzer /* INST_NAME */ (
|
||||
.clk(clk),
|
||||
|
||||
.addr_i(),
|
||||
.wdata_i(),
|
||||
.rdata_i(),
|
||||
.rw_i(),
|
||||
.valid_i(),
|
||||
|
||||
/* NET_CONNS */
|
||||
|
||||
.addr_o(),
|
||||
.wdata_o(),
|
||||
.rdata_o(),
|
||||
.rw_o(),
|
||||
.valid_o());
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
lut_ram #(.DEPTH(/* DEPTH */)) /* INST_NAME */ (
|
||||
.clk(clk),
|
||||
|
||||
.addr_i(),
|
||||
.wdata_i(),
|
||||
.rdata_i(),
|
||||
.rw_i(),
|
||||
.valid_i(),
|
||||
|
||||
.addr_o(),
|
||||
.wdata_o(),
|
||||
.rdata_o(),
|
||||
.rw_o(),
|
||||
.valid_o());
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
/* OP_DEC */
|
||||
/* ARG_DEC */
|
||||
/* TRIG_DEC */
|
||||
|
||||
trigger #(.INPUT_WIDTH(/* INPUT_WIDTH */)) /* NAME */ (
|
||||
.clk(clk),
|
||||
|
||||
.probe(/* PROBE */),
|
||||
.op(/* OP */),
|
||||
.arg(/* ARG */),
|
||||
.trig(/* TRIG */)
|
||||
);
|
||||
|
|
@ -5,7 +5,7 @@ module trigger_block (
|
|||
input wire clk,
|
||||
|
||||
// probes
|
||||
// @PROBE_PORTS
|
||||
/* PROBE_PORTS */
|
||||
|
||||
// trigger
|
||||
output reg trig,
|
||||
|
|
@ -25,15 +25,15 @@ module trigger_block (
|
|||
output reg valid_o);
|
||||
|
||||
parameter BASE_ADDR = 0;
|
||||
localparam MAX_ADDR = // @MAX_ADDR;
|
||||
localparam MAX_ADDR = /* MAX_ADDR */;
|
||||
|
||||
// trigger configuration registers
|
||||
// - each probe gets an operation and a compare register
|
||||
// - at the end we OR them all together. along with any custom probes the user specs
|
||||
|
||||
// @TRIGGER_MODULE_INSTS
|
||||
/* TRIGGER_MODULE_INSTS */
|
||||
|
||||
// @COMBINE_INDIV_TRIGGERS
|
||||
/* COMBINE_INDIV_TRIGGERS */
|
||||
|
||||
// perform register operations
|
||||
always @(posedge clk) begin
|
||||
|
|
@ -49,14 +49,14 @@ module trigger_block (
|
|||
// reads
|
||||
if(valid_i && !rw_i) begin
|
||||
case (addr_i)
|
||||
// @READ_CASE_STATEMENT_BODY
|
||||
/* READ_CASE_STATEMENT_BODY */
|
||||
endcase
|
||||
end
|
||||
|
||||
// writes
|
||||
else if(valid_i && rw_i) begin
|
||||
case (addr_i)
|
||||
// @WRITE_CASE_STATEMENT_BODY
|
||||
/* WRITE_CASE_STATEMENT_BODY */
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
|
|
|||
|
|
@ -0,0 +1,19 @@
|
|||
rx_uart #(.CLOCKS_PER_BAUD(/* CLOCKS_PER_BAUD */)) urx (
|
||||
.i_clk(clk),
|
||||
.i_uart_rx(rx),
|
||||
.o_wr(urx_brx_axiv),
|
||||
.o_data(urx_brx_axid));
|
||||
|
||||
logic [7:0] urx_brx_axid;
|
||||
logic urx_brx_axiv;
|
||||
|
||||
bridge_rx brx (
|
||||
.clk(clk),
|
||||
|
||||
.rx_data(urx_brx_axid),
|
||||
.rx_valid(urx_brx_axiv),
|
||||
|
||||
.addr_o(),
|
||||
.wdata_o(),
|
||||
.rw_o(),
|
||||
.valid_o());
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
bridge_tx btx (
|
||||
.clk(clk),
|
||||
|
||||
.rdata_i(),
|
||||
.rw_i(),
|
||||
.valid_i(),
|
||||
|
||||
.ready_i(utx_btx_ready),
|
||||
.data_o(btx_utx_data),
|
||||
.valid_o(btx_utx_valid));
|
||||
|
||||
logic utx_btx_ready;
|
||||
logic btx_utx_valid;
|
||||
logic [7:0] btx_utx_data;
|
||||
|
||||
uart_tx #(.CLOCKS_PER_BAUD(/* CLOCKS_PER_BAUD */)) utx (
|
||||
.clk(clk),
|
||||
|
||||
.data(btx_utx_data),
|
||||
.valid(btx_utx_valid),
|
||||
.ready(utx_btx_ready),
|
||||
|
||||
.tx(tx));
|
||||
Loading…
Reference in New Issue