clean up inferred BRAM, trim whitespace

Makefile

@@ -1,8 +1,8 @@
-build: 
+build:
 	python3 -m build
 
 pypi_upload: build
-	python3 -m twine upload --repository testpypi dist/*	
+	python3 -m twine upload --repository testpypi dist/*
 
 lint:
 	python3 -m black src/manta/__init__.py
@@ -20,11 +20,11 @@ real_loc:
 test: auto_gen functional_sim
 
 # API Generation Tests
-auto_gen: 
+auto_gen:
 	python3 test/auto_gen/run_tests.py
 
 # Functional Simulation
-functional_sim: io_core_tb logic_analyzer_tb bit_fifo_tb bridge_rx_tb bridge_tx_tb fifo_tb lut_ram_tb uart_tb uart_tx_tb 
+functional_sim: io_core_tb logic_analyzer_tb bit_fifo_tb bridge_rx_tb bridge_tx_tb lut_ram_tb uart_tb uart_tx_tb
 
 io_core_tb:
 	iverilog -g2012 -o sim.out -y src/manta test/functional_sim/io_core_tb.sv
@@ -51,11 +51,6 @@ bridge_tx_tb:
 	vvp sim.out
 	rm sim.out
 
-fifo_tb:
-	iverilog -g2012 -o sim.out -y src/manta test/functional_sim/fifo_tb.sv 
-	vvp sim.out >> /dev/null # this one is noisy right now
-	rm sim.out
-
 lut_ram_tb:
 	iverilog -g2012 -o sim.out -y src/manta test/functional_sim/lut_ram_tb.sv
 	vvp sim.out
@@ -70,7 +65,7 @@ uart_tx_tb:
 	iverilog -g2012 -o sim.out -y src/manta test/functional_sim/uart_tx_tb.sv
 	vvp sim.out
 	rm sim.out
-	
+
 clean:
 	rm -f *.out *.vcd
 	rm -rf dist/

src/manta/__init__.py

@@ -547,13 +547,13 @@ class LogicAnalyzerCore:
         logic_analyzer_hdl = pkgutil.get_data(__name__, "logic_analyzer.v").decode()
         la_fsm_hdl = pkgutil.get_data(__name__, "la_fsm.v").decode()
         sample_mem_hdl = pkgutil.get_data(__name__, "sample_mem.v").decode()
-        xilinx_bram_hdl = pkgutil.get_data(__name__, "xilinx_true_dual_port_read_first_2_clock_ram.v").decode()
+        dual_port_bram_hdl = pkgutil.get_data(__name__, "dual_port_bram.v").decode()
         trigger_hdl = pkgutil.get_data(__name__, "trigger.v").decode()
 
         # generate trigger block
         trigger_block_hdl = self.generate_trigger_block()
 
-        return logic_analyzer_hdl + la_fsm_hdl + sample_mem_hdl + xilinx_bram_hdl + trigger_block_hdl + trigger_hdl
+        return logic_analyzer_hdl + la_fsm_hdl + sample_mem_hdl + dual_port_bram_hdl + trigger_block_hdl + trigger_hdl
 
     def hdl_top_level_ports(self):
         # this should return the probes that we want to connect to top-level, but as a list of verilog ports

src/manta/bit_fifo.v

@@ -14,7 +14,7 @@ module bit_fifo(
     parameter OWIDTH = 0;
 
     localparam BWIDTH = OWIDTH-1 + IWIDTH;
-    
+
     reg [OWIDTH-1:0] buffer;
     reg [$clog2(OWIDTH)-1:0] buffer_size;
 
@@ -31,10 +31,10 @@ module bit_fifo(
     reg [OWIDTH-1:0] joined_halves;
 
     always @(*) begin
-        mask = (1 << buffer_size) - 1; 
+        mask = (1 << buffer_size) - 1;
         top_half = (buffer & mask) << (OWIDTH - buffer_size);
         bottom_half = in >> (IWIDTH- (OWIDTH - buffer_size));
-        joined_halves = top_half | bottom_half; 
+        joined_halves = top_half | bottom_half;
     end
 
     always @(posedge clk) begin
@@ -53,7 +53,7 @@ module bit_fifo(
                 //      so what we put back in the buffer is purely what's left over
                 //      from our input data once we've sliced out what we need
                 buffer_size <= buffer_size + IWIDTH - OWIDTH;
-                
+
                 // compute buffer contents
                 buffer <= ( (1 << (buffer_size + IWIDTH - OWIDTH)) - 1 ) & in;
 
@@ -64,9 +64,9 @@ module bit_fifo(
                 $display("   top_half:    %b", top_half);
                 $display("   bottom_half: %b", bottom_half);
                 $display("   out:         %b \n", joined_halves);
-                */ 
+                */
 
-                // compute output 
+                // compute output
                 out <= joined_halves;
                 out_valid <= 1;
             end

src/manta/bridge_tx.v

@@ -23,7 +23,7 @@ logic [3:0] byte_counter;
 initial begin
     busy = 0;
     buffer = 0;
-    byte_counter = 0; 
+    byte_counter = 0;
     valid_o = 0;
 end
 
@@ -41,7 +41,7 @@ always @(posedge clk) begin
 
         if(ready_i) begin
             byte_counter <= byte_counter + 1;
-            
+
             if (byte_counter > 5) begin
                 byte_counter <= 0;
 
@@ -59,7 +59,7 @@ always @(*) begin
     case (byte_counter)
         0: data_o = PREAMBLE;
         1: data_o = (buffer[15:12] < 10) ? (buffer[15:12] + 8'h30) : (buffer[15:12] + 8'h41 - 'd10);
-        2: data_o = (buffer[11:8] < 10) ? (buffer[11:8] + 8'h30) : (buffer[11:8] + 8'h41 - 'd10); 
+        2: data_o = (buffer[11:8] < 10) ? (buffer[11:8] + 8'h30) : (buffer[11:8] + 8'h41 - 'd10);
         3: data_o = (buffer[7:4] < 10) ? (buffer[7:4] + 8'h30) : (buffer[7:4] + 8'h41 - 'd10);
         4: data_o = (buffer[3:0] < 10) ? (buffer[3:0] + 8'h30) : (buffer[3:0] + 8'h41 - 'd10);
         5: data_o = CR;

src/manta/dual_port_bram.v

@@ -0,0 +1,51 @@
+
+//  Xilinx True Dual Port RAM, Read First, Dual Clock
+//  This code implements a parameterizable true dual port memory (both ports can read and write).
+//  The behavior of this RAM is when data is written, the prior memory contents at the write
+//  address are presented on the output port.  If the output data is
+//  not needed during writes or the last read value is desired to be retained,
+//  it is suggested to use a no change RAM as it is more power efficient.
+//  If a reset or enable is not necessary, it may be tied off or removed from the code.
+
+//  Modified from the xilinx_true_dual_port_read_first_2_clock_ram verilog language template.
+
+module dual_port_bram #(
+    parameter RAM_WIDTH = 0,
+    parameter RAM_DEPTH = 0
+    ) (
+    input wire [$clog2(RAM_DEPTH-1)-1:0] addra,
+    input wire [$clog2(RAM_DEPTH-1)-1:0] addrb,
+    input wire [RAM_WIDTH-1:0] dina,
+    input wire [RAM_WIDTH-1:0] dinb,
+    input wire clka,
+    input wire clkb,
+    input wire wea,
+    input wire web,
+    output wire [RAM_WIDTH-1:0] douta,
+    output wire [RAM_WIDTH-1:0] doutb
+    );
+
+    reg [RAM_WIDTH-1:0] BRAM [RAM_DEPTH-1:0];
+    reg [RAM_WIDTH-1:0] ram_data_a = {RAM_WIDTH{1'b0}};
+    reg [RAM_WIDTH-1:0] ram_data_b = {RAM_WIDTH{1'b0}};
+
+    always @(posedge clka) begin
+        if (wea) BRAM[addra] <= dina;
+        ram_data_a <= BRAM[addra];
+    end
+
+    always @(posedge clkb) begin
+        if (web) BRAM[addrb] <= dinb;
+        ram_data_b <= BRAM[addrb];
+    end
+
+    // Add a 2 clock cycle read latency to improve clock-to-out timing
+    reg [RAM_WIDTH-1:0] douta_reg = {RAM_WIDTH{1'b0}};
+    reg [RAM_WIDTH-1:0] doutb_reg = {RAM_WIDTH{1'b0}};
+
+    always @(posedge clka) douta_reg <= ram_data_a;
+    always @(posedge clkb) doutb_reg <= ram_data_b;
+
+    assign douta = douta_reg;
+    assign doutb = doutb_reg;
+endmodule

src/manta/fifo.v

@@ -1,85 +0,0 @@
-`default_nettype none
-`timescale 1ns / 1ps
-
-module fifo (
-	input wire clk,
-	input wire bram_rst,
-
-	input wire [WIDTH - 1:0] in,
-	input wire in_valid,
-
-	output reg [WIDTH - 1:0] out,
-	input wire out_req,
-	output reg out_valid,
-
-	output reg [AW:0] size,
-	output reg empty,
-	output reg full
-	);
-
-	parameter WIDTH = 8;
-	parameter DEPTH = 4096;
-	localparam AW = $clog2(DEPTH);
-
-	reg [AW:0] write_pointer;
-	reg [AW:0] read_pointer;
-
-	initial begin
-		write_pointer = 0;
-		read_pointer = 0;
-	end
-
-	reg empty_int;
-	assign empty_int = (write_pointer[AW] == read_pointer[AW]);
-
-	reg full_or_empty;
-	assign full_or_empty = (write_pointer[AW-1:0] == read_pointer[AW-1:0]);
-
-	assign full = full_or_empty & !empty_int;
-	assign empty = full_or_empty & empty_int;
-	assign size = write_pointer - read_pointer;
-
-	reg out_valid_pip_0;
-	reg out_valid_pip_1;
-
-	always @(posedge clk) begin
-		if (in_valid && ~full)
-			write_pointer <= write_pointer + 1'd1;
-
-	 	if (out_req && ~empty) begin
-			read_pointer <= read_pointer + 1'd1;
-			out_valid_pip_0 <= out_req;
-			out_valid_pip_1 <= out_valid_pip_0;
-			out_valid <= out_valid_pip_1;
-		end
-	end
-
-	xilinx_true_dual_port_read_first_2_clock_ram #(
-		.RAM_WIDTH(WIDTH),
-		.RAM_DEPTH(DEPTH),
-		.RAM_PERFORMANCE("HIGH_PERFORMANCE")
-
-		) buffer (
-
-		// write port
-		.clka(clk),
-		.rsta(bram_rst),
-		.ena(1'b1),
-		.addra(write_pointer),
-		.dina(in),
-		.wea(in_valid),
-		.regcea(1'b1),
-		.douta(),
-
-		// read port
-		.clkb(clk),
-		.rstb(bram_rst),
-		.enb(1'b1),
-		.addrb(read_pointer),
-		.dinb(),
-		.web(1'b0),
-		.regceb(1'b1),
-		.doutb(out));
-	endmodule
-
-`default_nettype wire

src/manta/io_core.v

@@ -47,7 +47,7 @@ module io_core(
         rw_o <= rw_i;
         valid_o <= valid_i;
         rdata_o <= rdata_i;
-        
+
 
         // check if address is valid
         if( (valid_i) && (addr_i >= BASE_ADDR) && (addr_i <= BASE_ADDR + 7)) begin

src/manta/la_fsm.v

@@ -122,7 +122,7 @@ module la_fsm(
         end
 
 
-        // return to IDLE state if somehow we get to a state that doesn't exist 
+        // return to IDLE state if somehow we get to a state that doesn't exist
         else begin
             state <= IDLE;
         end

src/manta/logic_analyzer.v

@@ -4,7 +4,7 @@
 module logic_analyzer(
     input wire clk,
 
-    // probes  
+    // probes
     input wire larry,
     input wire curly,
     input wire moe,
@@ -49,7 +49,7 @@ module logic_analyzer(
         .rdata_o(fsm_trig_blk_rdata),
         .rw_o(fsm_trig_blk_rw),
         .valid_o(fsm_trig_blk_valid));
-    
+
     reg [15:0] fsm_trig_blk_addr;
     reg [15:0] fsm_trig_blk_wdata;
     reg [15:0] fsm_trig_blk_rdata;
@@ -61,19 +61,19 @@ module logic_analyzer(
     reg fifo_acquire;
     reg fifo_pop;
     reg fifo_clear;
-     
+
 
     // trigger block
     trigger_block #(.BASE_ADDR(BASE_ADDR + 3)) trig_blk(
         .clk(clk),
-        
+
         .larry(larry),
         .curly(curly),
         .moe(moe),
         .shemp(shemp),
 
         .trig(trig),
-        
+
         .addr_i(fsm_trig_blk_addr),
         .wdata_i(fsm_trig_blk_wdata),
         .rdata_i(fsm_trig_blk_rdata),

src/manta/lut_ram.v

@@ -31,12 +31,12 @@ always @(posedge clk) begin
     rw_o <= rw_i;
     valid_o <= valid_i;
     rdata_o <= rdata_i;
-    
+
 
     if(valid_i) begin
         // check if address is valid
         if( (addr_i >= BASE_ADDR) && (addr_i <= BASE_ADDR + DEPTH - 1) ) begin
-            
+
             // read/write
             if (rw_i && !READ_ONLY) mem[addr_i - BASE_ADDR] <= wdata_i;
             else rdata_o <= mem[addr_i - BASE_ADDR];

src/manta/rx_uart.v

@@ -99,7 +99,7 @@ module rx_uart(
 				state <= IDLE;
 				baud_counter <= 0;
 			end
-		end 
+		end
 
 		else baud_counter <= baud_counter - 1'b1;
 

src/manta/sample_mem.v

@@ -81,31 +81,22 @@ module sample_mem(
 
     
     // bram
-    xilinx_true_dual_port_read_first_2_clock_ram #(
+    dual_port_bram #(
 		.RAM_WIDTH(16),
-		.RAM_DEPTH(SAMPLE_DEPTH),
-		.RAM_PERFORMANCE("HIGH_PERFORMANCE")
-
+		.RAM_DEPTH(SAMPLE_DEPTH)
     ) bram (
-
 		// read port (controlled by bus)
 		.clka(clk),
-		.rsta(1'b0),
-		.ena(1'b1),
 		.addra(bram_read_addr),
 		.dina(16'b0),
 		.wea(1'b0),
-		.regcea(1'b1),
 		.douta(bram_read_data),
 
 		// write port (controlled by FIFO)
 		.clkb(clk),
-		.rstb(1'b0),
-		.enb(1'b1),
 		.addrb(write_pointer[BRAM_ADDR_WIDTH-1:0]),
 		.dinb({9'b0, larry, curly, moe, shemp}),
 		.web(acquire),
-		.regceb(1'b1),
 		.doutb());
 
 

src/manta/trigger.v

@@ -3,7 +3,7 @@
 
 module trigger(
     input wire clk,
-    
+
     input wire [INPUT_WIDTH-1:0] probe,
     input wire [3:0] op,
     input wire [INPUT_WIDTH-1:0] arg,
@@ -38,7 +38,7 @@ module trigger(
             LEQ:        trig = (probe <= arg);
             EQ:         trig = (probe == arg);
             NEQ:        trig = (probe != arg);
-            default:    trig = 0; 
+            default:    trig = 0;
         endcase
     end
 endmodule

src/manta/trigger_block_template.v

@@ -30,7 +30,7 @@ module trigger_block (
     // trigger configuration registers
     // - each probe gets an operation and a compare register
     // - at the end we OR them all together. along with any custom probes the user specs
-    
+
     // @TRIGGER_MODULE_INSTS
 
     // @COMBINE_INDIV_TRIGGERS

src/manta/tx_uart.v

@@ -40,14 +40,14 @@
 //
 //
 module tx_uart(
-	input wire i_clk, 
+	input wire i_clk,
 	input wire i_wr,
-	input wire [7:0] i_data, 
-	output reg o_uart_tx, 
+	input wire [7:0] i_data,
+	output reg o_uart_tx,
 	output reg o_busy);
 
 	parameter	[23:0]	CLOCKS_PER_BAUD = 24'd868;
-	
+
 	// A line to tell others when we are ready to accept data.  If
 	// (i_wr)&&(!o_busy) is ever true, then the core has accepted a byte
 	// for transmission.

src/manta/uart_tx.v

@@ -3,7 +3,7 @@
 
 module uart_tx(
 	input wire clk,
-	
+
 	input wire [7:0] data,
 	input wire valid,
 	output reg busy,
@@ -11,7 +11,7 @@ module uart_tx(
 
 	output reg tx);
 
-	// this transmitter only works with 8N1 serial, at configurable baudrate	
+	// this transmitter only works with 8N1 serial, at configurable baudrate
 	parameter CLOCKS_PER_BAUD = 868;
 
 	reg [9:0] baud_counter;
@@ -57,7 +57,7 @@ module uart_tx(
 						busy <= 0;
 						ready <= 1;
 					end
-					// if valid happens here then we should bool 
+					// if valid happens here then we should bool
 				end
 
 				else begin
@@ -68,7 +68,7 @@ module uart_tx(
 		end
 	end
 
-	
+
 
 endmodule
 

src/manta/xilinx_true_dual_port_read_first_2_clock_ram.v

@@ -1,119 +0,0 @@
-
-//  Xilinx True Dual Port RAM, Read First, Dual Clock
-//  This code implements a parameterizable true dual port memory (both ports can read and write).
-//  The behavior of this RAM is when data is written, the prior memory contents at the write
-//  address are presented on the output port.  If the output data is
-//  not needed during writes or the last read value is desired to be retained,
-//  it is suggested to use a no change RAM as it is more power efficient.
-//  If a reset or enable is not necessary, it may be tied off or removed from the code.
-
-module xilinx_true_dual_port_read_first_2_clock_ram #(
-  parameter RAM_WIDTH = 18,                       // Specify RAM data width
-  parameter RAM_DEPTH = 1024,                     // Specify RAM depth (number of entries)
-  parameter RAM_PERFORMANCE = "HIGH_PERFORMANCE", // Select "HIGH_PERFORMANCE" or "LOW_LATENCY"
-  parameter INIT_FILE = ""                        // Specify name/location of RAM initialization file if using one (leave blank if not)
-) (
-  input [clogb2(RAM_DEPTH-1)-1:0] addra,  // Port A address bus, width determined from RAM_DEPTH
-  input [clogb2(RAM_DEPTH-1)-1:0] addrb,  // Port B address bus, width determined from RAM_DEPTH
-  input [RAM_WIDTH-1:0] dina,           // Port A RAM input data
-  input [RAM_WIDTH-1:0] dinb,           // Port B RAM input data
-  input clka,                           // Port A clock
-  input clkb,                           // Port B clock
-  input wea,                            // Port A write enable
-  input web,                            // Port B write enable
-  input ena,                            // Port A RAM Enable, for additional power savings, disable port when not in use
-  input enb,                            // Port B RAM Enable, for additional power savings, disable port when not in use
-  input rsta,                           // Port A output reset (does not affect memory contents)
-  input rstb,                           // Port B output reset (does not affect memory contents)
-  input regcea,                         // Port A output register enable
-  input regceb,                         // Port B output register enable
-  output [RAM_WIDTH-1:0] douta,         // Port A RAM output data
-  output [RAM_WIDTH-1:0] doutb          // Port B RAM output data
-);
-
-  reg [RAM_WIDTH-1:0] BRAM [RAM_DEPTH-1:0];
-  reg [RAM_WIDTH-1:0] ram_data_a = {RAM_WIDTH{1'b0}};
-  reg [RAM_WIDTH-1:0] ram_data_b = {RAM_WIDTH{1'b0}};
-
-  //this loop below allows for rendering with iverilog simulations!
-  /*
-  integer idx;
-  for(idx = 0; idx < RAM_DEPTH; idx = idx+1) begin: cats
-    wire [RAM_WIDTH-1:0] tmp;
-    assign tmp = BRAM[idx];
-  end
-  */
-
-  // The following code either initializes the memory values to a specified file or to all zeros to match hardware
-  generate
-    if (INIT_FILE != "") begin: use_init_file
-      initial
-        $readmemh(INIT_FILE, BRAM, 0, RAM_DEPTH-1);
-    end else begin: init_bram_to_zero
-      integer ram_index;
-      initial
-        for (ram_index = 0; ram_index < RAM_DEPTH; ram_index = ram_index + 1)
-          BRAM[ram_index] = {RAM_WIDTH{1'b0}};
-    end
-  endgenerate
-  integer idx;
-  // initial begin
-  //   for (idx = 0; idx < RAM_DEPTH; idx = idx + 1) begin
-  //     $dumpvars(0, BRAM[idx]);
-  //   end
-  // end
-  always @(posedge clka)
-    if (ena) begin
-      if (wea)
-        BRAM[addra] <= dina;
-      ram_data_a <= BRAM[addra];
-    end
-
-  always @(posedge clkb)
-    if (enb) begin
-      if (web)
-        BRAM[addrb] <= dinb;
-      ram_data_b <= BRAM[addrb];
-    end
-
-  //  The following code generates HIGH_PERFORMANCE (use output register) or LOW_LATENCY (no output register)
-  generate
-    if (RAM_PERFORMANCE == "LOW_LATENCY") begin: no_output_register
-
-      // The following is a 1 clock cycle read latency at the cost of a longer clock-to-out timing
-       assign douta = ram_data_a;
-       assign doutb = ram_data_b;
-
-    end else begin: output_register
-
-      // The following is a 2 clock cycle read latency with improve clock-to-out timing
-
-      reg [RAM_WIDTH-1:0] douta_reg = {RAM_WIDTH{1'b0}};
-      reg [RAM_WIDTH-1:0] doutb_reg = {RAM_WIDTH{1'b0}};
-
-      always @(posedge clka)
-        if (rsta)
-          douta_reg <= {RAM_WIDTH{1'b0}};
-        else if (regcea)
-          douta_reg <= ram_data_a;
-
-      always @(posedge clkb)
-        if (rstb)
-          doutb_reg <= {RAM_WIDTH{1'b0}};
-        else if (regceb)
-          doutb_reg <= ram_data_b;
-
-      assign douta = douta_reg;
-      assign doutb = doutb_reg;
-
-    end
-  endgenerate
-
-  //  The following function calculates the address width based on specified RAM depth
-  function integer clogb2;
-    input integer depth;
-      for (clogb2=0; depth>0; clogb2=clogb2+1)
-        depth = depth >> 1;
-  endfunction
-
-endmodule

test/functional_sim/bit_fifo_tb.sv

@@ -65,7 +65,7 @@ module bit_fifo_tb;
         #(10*`CP);
         in_valid = 0;
         en = 0;
-        
+
         #(10*`CP);
         /* ==== Test 2 End ==== */
         $finish();

test/functional_sim/bridge_rx_tb.sv

@@ -21,7 +21,7 @@ logic rst;
 string message;
 integer test_num;
 
-// uart inputs and outputs 
+// uart inputs and outputs
 logic rx;
 logic [7:0] rx_data;
 logic rx_valid;
@@ -43,7 +43,7 @@ bridge_rx bridge_rx_uut(
     // connect to uart_rx
     .rx_data(rx_data),
     .rx_valid(rx_valid),
-    
+
     .addr_o(addr),
     .wdata_o(wdata),
     .rw_o(rw),
@@ -107,7 +107,7 @@ initial begin
     assert(bridge_rx_uut.state != bridge_rx_uut.ERROR) else $error("in error state before transmission");
     message = {"MBABE", 8'h0D, 8'h0A};
     `SEND_MESSAGE(message)
-    
+
     assert(addr == 16'hBABE) else $error("incorrect addr!");
     assert(rw == 0) else $error("incorrect rw!");
     assert(bridge_rx_uut.state != bridge_rx_uut.ERROR) else $error("in error state after transmission");
@@ -121,7 +121,7 @@ initial begin
     assert(bridge_rx_uut.state != bridge_rx_uut.ERROR) else $error("in error state before transmission");
     message = {"M0000", 8'h0D};
     `SEND_MESSAGE(message)
-    
+
     assert(addr == 16'h0000) else $error("incorrect addr!");
     assert(rw == 0) else $error("incorrect rw!");
     assert(bridge_rx_uut.state != bridge_rx_uut.ERROR) else $error("in error state after transmission");
@@ -135,7 +135,7 @@ initial begin
     assert(bridge_rx_uut.state != bridge_rx_uut.ERROR) else $error("in error state before transmission");
     message = {"M1234", 8'h0D};
     `SEND_MESSAGE(message)
-    
+
     assert(addr == 16'h1234) else $error("incorrect addr!");
     assert(rw == 0) else $error("incorrect rw!");
     assert(bridge_rx_uut.state != bridge_rx_uut.ERROR) else $error("in error state after transmission");
@@ -149,7 +149,7 @@ initial begin
     assert(bridge_rx_uut.state != bridge_rx_uut.ERROR) else $error("in error state before transmission");
     message = {"MF00DBEEF", 8'h0D};
     `SEND_MESSAGE(message)
-    
+
     assert(addr == 16'hF00D) else $error("incorrect addr!");
     assert(wdata == 16'hBEEF) else $error("incorrect data!");
     assert(rw == 1) else $error("incorrect rw!");
@@ -164,7 +164,7 @@ initial begin
     assert(bridge_rx_uut.state != bridge_rx_uut.ERROR) else $error("in error state before transmission");
     message = {"MB0BACAFE", 8'h0D};
     `SEND_MESSAGE(message)
-    
+
     assert(addr == 16'hB0BA) else $error("incorrect addr!");
     assert(wdata == 16'hCAFE) else $error("incorrect data!");
     assert(rw == 1) else $error("incorrect rw!");
@@ -180,7 +180,7 @@ initial begin
     assert(bridge_rx_uut.state != bridge_rx_uut.ERROR) else $error("in error state before transmission");
     message = {"MABC", 8'h0D, 8'h0A};
     `SEND_MESSAGE(message)
-    
+
     assert(valid == 0) else $error("valid asserted for bad message");
     assert(bridge_rx_uut.state == bridge_rx_uut.ERROR) else $error("not in error state after transmission");
 
@@ -195,7 +195,7 @@ initial begin
     assert(bridge_rx_uut.state != bridge_rx_uut.ERROR) else $error("in error state before transmission");
     message = {"MABC", 8'h0D, 8'h0A};
     `SEND_MESSAGE(message)
-    
+
     assert(valid == 0) else $error("valid asserted for bad message");
     assert(bridge_rx_uut.state == bridge_rx_uut.ERROR) else $error("not in error state after transmission");
 
@@ -210,7 +210,7 @@ initial begin
     assert(bridge_rx_uut.state != bridge_rx_uut.ERROR) else $error("in error state before transmission");
     message = {"MABC", 8'h0D, 8'h0A};
     `SEND_MESSAGE(message)
-    
+
     assert(valid == 0) else $error("valid asserted for bad message");
     assert(bridge_rx_uut.state == bridge_rx_uut.ERROR) else $error("not in error state after transmission");
 
@@ -225,7 +225,7 @@ initial begin
     assert(bridge_rx_uut.state != bridge_rx_uut.ERROR) else $error("in error state before transmission");
     message = {"MABC", 8'h0D, 8'h0A};
     `SEND_MESSAGE(message)
-    
+
     assert(valid == 0) else $error("valid asserted for bad message");
     assert(bridge_rx_uut.state == bridge_rx_uut.ERROR) else $error("not in error state after transmission");
 
@@ -240,7 +240,7 @@ initial begin
     assert(bridge_rx_uut.state != bridge_rx_uut.ERROR) else $error("in error state before transmission");
     message = {"MABCG", 8'h0D, 8'h0A};
     `SEND_MESSAGE(message)
-    
+
     assert(valid == 0) else $error("valid asserted for bad message");
     assert(bridge_rx_uut.state == bridge_rx_uut.ERROR) else $error("not in error state after transmission");
 
@@ -255,7 +255,7 @@ initial begin
     assert(bridge_rx_uut.state != bridge_rx_uut.ERROR) else $error("in error state before transmission");
     message = {"MABC[]()##*@", 8'h0D, 8'h0A};
     `SEND_MESSAGE(message)
-    
+
     assert(valid == 0) else $error("valid asserted for bad message");
     assert(bridge_rx_uut.state == bridge_rx_uut.ERROR) else $error("not in error state after transmission");
 
@@ -270,7 +270,7 @@ initial begin
     assert(bridge_rx_uut.state != bridge_rx_uut.ERROR) else $error("in error state before transmission");
     message = {"M", 8'h0D, 8'h0A};
     `SEND_MESSAGE(message)
-    
+
     assert(valid == 0) else $error("valid asserted for bad message");
     assert(bridge_rx_uut.state == bridge_rx_uut.ERROR) else $error("not in error state after transmission");
 

test/functional_sim/bridge_tx_tb.sv

@@ -44,7 +44,7 @@ uart_tx #(
     .valid(btx_utx_valid),
     .busy(),
     .ready(btx_utx_ready),
-    
+
     .tx(utx_tb_tx));
 
 always begin
@@ -69,7 +69,7 @@ initial begin
     test_num = 1;
     tb_btx_rdata = 16'h0123;
     tb_btx_valid = 1;
-    
+
     #`CP;
     assert(res_ready == 0) else $error("invalid handshake: res_ready held high for more than one clock cycle");
     tb_btx_valid = 0;
@@ -82,7 +82,7 @@ initial begin
     test_num = 2;
     tb_btx_rdata = 16'h4567;
     tb_btx_valid = 1;
-    
+
     #`CP;
     assert(res_ready == 0) else $error("invalid handshake: res_ready held high for more than one clock cycle");
     tb_btx_valid = 0;
@@ -95,7 +95,7 @@ initial begin
     test_num = 3;
     tb_btx_rdata = 16'h89AB;
     tb_btx_valid = 1;
-    
+
     #`CP;
     assert(res_ready == 0) else $error("invalid handshake: res_ready held high for more than one clock cycle");
     tb_btx_valid = 0;
@@ -108,7 +108,7 @@ initial begin
     test_num = 4;
     tb_btx_rdata = 16'hCDEF;
     tb_btx_valid = 1;
-    
+
     #`CP;
     assert(res_ready == 0) else $error("invalid handshake: res_ready held high for more than one clock cycle");
     tb_btx_valid = 0;

test/functional_sim/bus_fix_tb.sv

@@ -72,15 +72,15 @@ module bus_fix_tb;
         .rdata_o(mem_btx_rdata),
         .rw_o(mem_btx_rw),
         .valid_o(mem_btx_valid));
-    
-    // mem --> frizzle signals, it's frizzle because that's a bus you wanna get off of 
+
+    // mem --> frizzle signals, it's frizzle because that's a bus you wanna get off of
     logic [15:0] mem_btx_rdata;
     logic mem_btx_rw;
     logic mem_btx_valid;
 
     bridge_tx btx (
         .clk(clk),
-        
+
         .rdata_i(mem_btx_rdata),
         .rw_i(mem_btx_rw),
         .valid_i(mem_btx_valid),
@@ -92,7 +92,7 @@ module bus_fix_tb;
     logic utx_btx_ready;
     logic btx_utx_valid;
     logic [7:0] btx_utx_data;
-    
+
     uart_tx #(.CLOCKS_PER_BAUD(CLOCKS_PER_BAUD)) utx (
         .clk(clk),
 
@@ -140,7 +140,7 @@ module bus_fix_tb;
         #`HCP
 
         // throw some nonzero data in the memories just so we know that we're pulling from the right ones
-        
+
         for(int i=0; i< 32; i++) mem.mem[i] = i;
 
         #(10*`CP);
@@ -149,7 +149,7 @@ module bus_fix_tb;
         $display("\n=== test 1: write 0x5678 to 0x1234 for baseline functionality ===");
         test_num = 1;
         msg = {"M1234", 8'h0D, 8'h0A};
-        `SEND_MSG_BITS(msg) 
+        `SEND_MSG_BITS(msg)
 
         #(10*`CP);
         /* ==== Test 1 End ==== */
@@ -158,7 +158,7 @@ module bus_fix_tb;
         $display("\n=== test 2: read from 0x0001 for baseline functionality ===");
         test_num = 2;
         msg = {"M1234", 8'h0D, 8'h0A};
-        `SEND_MSG_BITS(msg) 
+        `SEND_MSG_BITS(msg)
 
         #(1000*`CP);
         /* ==== Test 2 End ==== */
@@ -183,7 +183,7 @@ module bus_fix_tb;
         //     msg = {$sformatf("M%H", j), 8'h0D, 8'h0A};
         //     `SEND_MSG_BITS(msg)
         // end
-        
+
 
         #(10*`CP);
         /* ==== Test 3 End ==== */
@@ -196,7 +196,7 @@ module bus_fix_tb;
             msg = {"M12345678", 8'h0D, 8'h0A};
             `SEND_MSG_BITS(msg);
         end
- 
+
         /* ==== Test 4 End ==== */
 
         /* ==== Test 5 Begin ==== */
@@ -207,11 +207,11 @@ module bus_fix_tb;
             msg = {"M1234", 8'h0D, 8'h0A};
             `SEND_MSG_BITS(msg);
         end
- 
+
         /* ==== Test 5 End ==== */
 
 
-        
+
         #(1000*`CP)
 
         $finish();

test/functional_sim/fifo_tb.sv

@@ -1,70 +0,0 @@
-`default_nettype none
-`timescale 1ns / 1ps
-
-module fifo_tb();
-	logic clk;
-	logic rst;
-
-	logic [7:0] in;
-	logic in_valid;
-	
-	logic out_req;
-	logic [7:0] out;
-
-	logic [11:0] size;
-	logic empty;
-	logic full;
-
-	fifo uut (
-		.clk(clk),
-		.bram_rst(rst),
-	
-		.in(in),
-		.in_valid(in_valid),
-		
-		.out_req(out_req),
-		.out(out),
-
-		.size(size),
-		.empty(empty),
-		.full(full));
-
-  	always begin
-    		#5;
-    		clk = !clk;
-  	end
-
-  	initial begin
-    		$dumpfile("fifo.vcd");
-    		$dumpvars(0, fifo_tb);
-		clk = 0;
-		rst = 1;
-		in = 0;
-		in_valid = 0;
-		out_req = 0;
-		#10;
-		rst = 0;
-		#10;
-
-		// try and load some data, make sure counter increases
-		in_valid = 1;
-
-		for(int i=0; i < 4097; i++) begin
-			in = i;
-			#10;
-		end
-		
-		in_valid = 0;
-
-		// try and read out said data
-		out_req = 1;
-		for(int i=0; i < 4097; i++) begin
-			$display("%h", out);
-			#10;
-		end
-
-		$finish();
-	end
-endmodule
-
-`default_nettype wire

test/functional_sim/io_core_tb.sv

@@ -39,11 +39,11 @@ module io_core_tb;
     io_core #(.BASE_ADDR(0), .SAMPLE_DEPTH(128)) io(
         .clk(clk),
 
-        // inputs 
+        // inputs
         .picard(picard),
         .data(data),
         .laforge(laforge),
-        .troi(troi),     
+        .troi(troi),
 
         // outputs
         .kirk(kirk),
@@ -88,7 +88,7 @@ module io_core_tb;
         data = 0;
         laforge = 0;
         troi = 0;
-        
+
         #`HCP
         #(10*`CP);
 
@@ -106,7 +106,7 @@ module io_core_tb;
 
         #(10*`CP);
         /* ==== Test 1 End ==== */
-        
+
         $finish();
     end
 endmodule

test/functional_sim/logic_analyzer_tb.sv

@@ -203,7 +203,7 @@ module logic_analyzer_tb;
         write_and_verify(8, 1, "moe_arg");
         write_and_verify(8, 0, "moe_arg");
 
-        // shemp 
+        // shemp
         write_and_verify(9, 0, "shemp_op");
         write_and_verify(9, 7, "shemp_op");
         write_and_verify(9, 0, "shemp_op");
@@ -221,7 +221,7 @@ module logic_analyzer_tb;
         $display("\n=== test 3: verify FSM doesn't move out of IDLE when not running ===");
         test_num = 3;
 
-        write_and_verify(3, 8, "larry_op");  // set operation to  eq 
+        write_and_verify(3, 8, "larry_op");  // set operation to  eq
         write_and_verify(4, 1, "larry_arg"); // set argument to 1
 
         // set larry = 1, verify core doesn't trigger
@@ -230,10 +230,10 @@ module logic_analyzer_tb;
 
         $display(" -> la core is in state 0x%h", la.fsm.state);
         assert(la.fsm.state == la.fsm.IDLE) else $error("core moved outside of IDLE state when not running!");
-        
+
         $display(" -> wait a clock cycle");
         #`CP
-        
+
         $display(" -> la core is in state 0x%h", la.fsm.state);
         assert(la.fsm.state == la.fsm.IDLE) else $error("core moved outside of IDLE state when not running!");
 
@@ -280,15 +280,15 @@ module logic_analyzer_tb;
 
         write_and_verify(9, 6, "shemp_op");   // set operation to GT
         write_and_verify(10, 3, "shemp_arg"); // set argument to 3
-        
-        assert( (la.fsm.state == la.fsm.IDLE) || (la.fsm.state == la.fsm.FILLED) ) 
+
+        assert( (la.fsm.state == la.fsm.IDLE) || (la.fsm.state == la.fsm.FILLED) )
             else $error("core is running when it shouldn't be!");
 
         larry = 0;
         curly = 0;
         moe = 0;
         shemp = 0;
-         
+
         write_reg(0, la.fsm.START_CAPTURE, "state");
 
         shemp = 4;

test/functional_sim/lut_ram_tb.sv

@@ -42,7 +42,7 @@ module lut_ram_tb;
     logic mem_1_mem_2_rw;
     logic mem_1_mem_2_valid;
 
-    lut_ram #( 
+    lut_ram #(
         .DEPTH(8),
         .BASE_ADDR(8)
     ) mem_2 (
@@ -199,7 +199,7 @@ module lut_ram_tb;
         tb_mem_1_valid = 0;
         #(10*`CP);
         /* ==== Test 3 End ==== */
-        
+
         $finish();
     end
 endmodule

test/functional_sim/uart_tx_tb.sv

@@ -23,15 +23,15 @@ module uart_tx_tb();
 		.tx(utx_tb_tx));
 
 
-	logic zcpu_tb_tx; 
+	logic zcpu_tb_tx;
 	logic zcpu_tb_busy;
-	
+
 	tx_uart #(.CLOCKS_PER_BAUD(10)) zcpu_utx (
 		.i_clk(clk),
 
 		.i_wr(tb_utx_valid),
 		.i_data(tb_utx_data),
-		
+
 		.o_uart_tx(zcpu_tb_tx),
 		.o_busy(zcpu_tb_busy));
 
@@ -83,7 +83,7 @@ module uart_tx_tb();
 		tb_utx_valid = 0;
 
 		#(99*`CP);
-		
+
 		tb_utx_data = 8'h42;
 		tb_utx_valid = 1;
 		#`CP;
@@ -97,7 +97,7 @@ module uart_tx_tb();
 		#`CP;
 
 		#(99*`CP);
-		
+
 		tb_utx_data = 8'h42;
 		tb_utx_valid = 1;
 		#`CP;