rename files, remove reference to ILA
This commit is contained in:
Fischer Moseley
parent
b11f07857a
commit
ae89e9a778
|
|
@ -18,7 +18,7 @@ jobs:
|
|||
echo "${{ secrets.LAB_BC_KNOWN_HOSTS }}" > ~/.ssh/known_hosts
|
||||
|
||||
- name: Generate Core
|
||||
run: python3 manta.py gen examples/counter/ila.yaml examples/counter/src/debug.sv
|
||||
run: python3 manta.py gen examples/counter/manta.yaml examples/counter/src/debug.sv
|
||||
|
||||
- name: Build Verilog
|
||||
working-directory: examples/counter
|
||||
|
|
|
|||
|
|
@ -1,23 +0,0 @@
|
|||
{
|
||||
"downlink": {
|
||||
"sample_depth": 4096,
|
||||
"clock_freq": 100000000,
|
||||
"probes": {
|
||||
"larry": 1,
|
||||
"curly": 1,
|
||||
"moe": 1,
|
||||
"shemp": 3
|
||||
},
|
||||
"triggers": [
|
||||
"larry && curly && ~moe"
|
||||
]
|
||||
},
|
||||
"uart": {
|
||||
"baudrate": 115200,
|
||||
"port": "/dev/tty.usbserial-2102926963071",
|
||||
"data": 8,
|
||||
"parity": "none",
|
||||
"stop": 1,
|
||||
"timeout": 1
|
||||
}
|
||||
}
|
||||
|
|
@ -1,92 +1,8 @@
|
|||
`default_nettype none
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module fifo (
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
|
||||
input wire [WIDTH - 1:0] data_in,
|
||||
input wire input_ready,
|
||||
|
||||
input wire request_output,
|
||||
output logic [WIDTH - 1:0] data_out,
|
||||
output logic output_valid,
|
||||
|
||||
output logic [AW:0] size,
|
||||
output logic empty,
|
||||
output logic full
|
||||
);
|
||||
|
||||
parameter WIDTH = 8;
|
||||
parameter DEPTH = 4096;
|
||||
localparam AW = $clog2(DEPTH);
|
||||
|
||||
logic [AW:0] write_pointer;
|
||||
logic [AW:0] read_pointer;
|
||||
|
||||
logic empty_int;
|
||||
assign empty_int = (write_pointer[AW] == read_pointer[AW]);
|
||||
|
||||
logic full_or_empty;
|
||||
assign full_or_empty = (write_pointer[AW-1:0] == read_pointer[AW-1:0]);
|
||||
|
||||
assign full = full_or_empty & !empty_int;
|
||||
assign empty = full_or_empty & empty_int;
|
||||
assign size = write_pointer - read_pointer;
|
||||
|
||||
logic output_valid_pip_0;
|
||||
logic output_valid_pip_1;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (input_ready && ~full)
|
||||
write_pointer <= write_pointer + 1'd1;
|
||||
|
||||
if (request_output && ~empty)
|
||||
read_pointer <= read_pointer + 1'd1;
|
||||
output_valid_pip_0 <= request_output;
|
||||
output_valid_pip_1 <= output_valid_pip_0;
|
||||
output_valid <= output_valid_pip_1;
|
||||
|
||||
if (rst) begin
|
||||
read_pointer <= 0;
|
||||
write_pointer <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
xilinx_true_dual_port_read_first_2_clock_ram #(
|
||||
.RAM_WIDTH(WIDTH),
|
||||
.RAM_DEPTH(DEPTH),
|
||||
.RAM_PERFORMANCE("HIGH_PERFORMANCE")
|
||||
|
||||
) buffer (
|
||||
|
||||
// write port
|
||||
.clka(clk),
|
||||
.rsta(rst),
|
||||
.ena(1),
|
||||
.addra(write_pointer),
|
||||
.dina(data_in),
|
||||
.wea(input_ready),
|
||||
.regcea(1),
|
||||
.douta(),
|
||||
|
||||
// read port
|
||||
.clkb(clk),
|
||||
.rstb(rst),
|
||||
.enb(1),
|
||||
.addrb(read_pointer),
|
||||
.dinb(),
|
||||
.web(0),
|
||||
.regceb(1),
|
||||
.doutb(data_out));
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
`default_nettype none
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
This ILA was autogenerated on 09 Feb 2023 at 15:05:46 by fischerm
|
||||
This manta definition was autogenerated on 09 Feb 2023 at 15:26:40 by fischerm
|
||||
|
||||
If this breaks or if you've got dank formal verification memes,
|
||||
please contact fischerm [at] mit.edu.
|
||||
|
|
@ -99,7 +15,7 @@ please contact fischerm [at] mit.edu.
|
|||
|
||||
`define ARM_BYTE 8'b00110000
|
||||
|
||||
module ila (
|
||||
module manta (
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
|
||||
|
|
@ -311,6 +227,90 @@ endmodule
|
|||
`default_nettype wire`default_nettype none
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module fifo (
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
|
||||
input wire [WIDTH - 1:0] data_in,
|
||||
input wire input_ready,
|
||||
|
||||
input wire request_output,
|
||||
output logic [WIDTH - 1:0] data_out,
|
||||
output logic output_valid,
|
||||
|
||||
output logic [AW:0] size,
|
||||
output logic empty,
|
||||
output logic full
|
||||
);
|
||||
|
||||
parameter WIDTH = 8;
|
||||
parameter DEPTH = 4096;
|
||||
localparam AW = $clog2(DEPTH);
|
||||
|
||||
logic [AW:0] write_pointer;
|
||||
logic [AW:0] read_pointer;
|
||||
|
||||
logic empty_int;
|
||||
assign empty_int = (write_pointer[AW] == read_pointer[AW]);
|
||||
|
||||
logic full_or_empty;
|
||||
assign full_or_empty = (write_pointer[AW-1:0] == read_pointer[AW-1:0]);
|
||||
|
||||
assign full = full_or_empty & !empty_int;
|
||||
assign empty = full_or_empty & empty_int;
|
||||
assign size = write_pointer - read_pointer;
|
||||
|
||||
logic output_valid_pip_0;
|
||||
logic output_valid_pip_1;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (input_ready && ~full)
|
||||
write_pointer <= write_pointer + 1'd1;
|
||||
|
||||
if (request_output && ~empty)
|
||||
read_pointer <= read_pointer + 1'd1;
|
||||
output_valid_pip_0 <= request_output;
|
||||
output_valid_pip_1 <= output_valid_pip_0;
|
||||
output_valid <= output_valid_pip_1;
|
||||
|
||||
if (rst) begin
|
||||
read_pointer <= 0;
|
||||
write_pointer <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
xilinx_true_dual_port_read_first_2_clock_ram #(
|
||||
.RAM_WIDTH(WIDTH),
|
||||
.RAM_DEPTH(DEPTH),
|
||||
.RAM_PERFORMANCE("HIGH_PERFORMANCE")
|
||||
|
||||
) buffer (
|
||||
|
||||
// write port
|
||||
.clka(clk),
|
||||
.rsta(rst),
|
||||
.ena(1),
|
||||
.addra(write_pointer),
|
||||
.dina(data_in),
|
||||
.wea(input_ready),
|
||||
.regcea(1),
|
||||
.douta(),
|
||||
|
||||
// read port
|
||||
.clkb(clk),
|
||||
.rstb(rst),
|
||||
.enb(1),
|
||||
.addrb(read_pointer),
|
||||
.dinb(),
|
||||
.web(0),
|
||||
.regceb(1),
|
||||
.doutb(data_out));
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
`default_nettype none
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
|
||||
module uart_tx(
|
||||
input wire clk,
|
||||
|
|
|
|||
|
|
@ -16,9 +16,8 @@ module top_level (
|
|||
logic [7:0] count;
|
||||
always_ff @(posedge clk) count <= count + 1;
|
||||
|
||||
// ILA
|
||||
// later make this a #ILA that gets loaded from a svh file that the python script generates
|
||||
ila ila(
|
||||
// debugger
|
||||
manta manta(
|
||||
.clk(clk),
|
||||
.rst(btnc),
|
||||
.larry(count[0]),
|
||||
|
|
|
|||
7
manta.py
7
manta.py
|
|
@ -11,12 +11,17 @@ version = "0.0.0"
|
|||
|
||||
|
||||
def load_source_files(path):
|
||||
"""concatenates the list of files provided into a single string"""
|
||||
"""concatenates the contents of the list of files provided into a single string"""
|
||||
source_files = [
|
||||
f for f in os.listdir(path) if os.path.isfile(os.path.join(path, f))
|
||||
]
|
||||
source_files = [f for f in source_files if f.split(".")[-1] in ["sv", "v"]]
|
||||
|
||||
# bring manta_template.sv to the top, if it exists
|
||||
print(source_files)
|
||||
if "manta_template.sv" in source_files:
|
||||
source_files.insert(0, source_files.pop(source_files.index("manta_template.sv")))
|
||||
|
||||
buf = ""
|
||||
for source_file in source_files:
|
||||
with open(path + source_file, "r") as f:
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
This ILA was autogenerated on @TIMESTAMP by @USER
|
||||
This manta definition was autogenerated on @TIMESTAMP by @USER
|
||||
|
||||
If this breaks or if you've got dank formal verification memes,
|
||||
please contact fischerm [at] mit.edu.
|
||||
|
|
@ -15,7 +15,7 @@ please contact fischerm [at] mit.edu.
|
|||
|
||||
`define ARM_BYTE 8'b00110000
|
||||
|
||||
module ila (
|
||||
module manta (
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
|
||||
Loading…
Reference in New Issue