add prototype simulation replay
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Fischer Moseley
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@ -1,4 +1,14 @@
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from manta import Manta
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import pickle
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m = Manta('manta.yaml')
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print(m.my_logic_analyzer.run())
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# capture = m.my_logic_analyzer.capture()
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# with open("capture.pkl", "wb") as f:
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# pickle.dump(capture, f)
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with open("capture.pkl", "rb") as f:
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capture = pickle.load(f)
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m.my_logic_analyzer.export_vcd(capture, "capture.vcd")
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m.my_logic_analyzer.export_mem(capture, "capture.mem")
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@ -0,0 +1,80 @@
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`default_nettype none
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`timescale 1ns/1ps
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module replay_tb();
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logic clk;
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always begin
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#5;
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clk = !clk;
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end
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logic larry;
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logic curly;
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logic moe;
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logic [3:0] shemp;
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my_logic_analyzer_playback playback (
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.clk(clk),
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.enable(1'b1),
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.done(),
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.larry(larry),
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.curly(curly),
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.moe(moe),
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.shemp(shemp));
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initial begin
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clk = 0;
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$dumpfile("replay_tb.vcd");
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$dumpvars(0, replay_tb);
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#(4500*5);
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$finish();
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end
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endmodule
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module my_logic_analyzer_playback (
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input wire clk,
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input wire enable,
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output reg done,
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output reg larry,
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output reg curly,
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output reg moe,
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output reg [3:0] shemp);
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localparam FILENAME = "capture.mem";
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localparam SAMPLE_DEPTH = 4096;
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localparam TOTAL_PROBE_WIDTH = 7;
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reg [TOTAL_PROBE_WIDTH-1:0] capture [SAMPLE_DEPTH-1:0];
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reg [$clog2(SAMPLE_DEPTH)-1:0] addr;
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reg [TOTAL_PROBE_WIDTH-1:0] sample;
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assign done = (addr >= SAMPLE_DEPTH);
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initial begin
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$display("Loading capture from %s", FILENAME);
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$readmemb(FILENAME, capture);
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addr = 0;
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end
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always @(posedge clk) begin
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if (enable && !done) begin
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addr = addr + 1;
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sample = capture[addr];
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larry = sample[0];
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curly = sample[1];
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moe = sample[2];
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shemp = sample[6:3];
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end
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end
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endmodule
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`default_nettype wire
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@ -14,7 +14,7 @@ module top_level (
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logic [3:0] shemp = 0;
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always_ff @(posedge clk) begin
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{larry, curly, moe, shemp} <= {larry, curly, moe, shemp} + 1;
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{shemp, moe, curly, larry} <= {shemp, moe, curly, larry} + 1;
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end
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manta manta_inst (
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@ -551,7 +551,15 @@ class LogicAnalyzerCore:
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la.sub(self.total_probe_width, "/* TOTAL_PROBE_WIDTH */")
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probes_concat = '{' + ', '.join(self.probes.keys()) + '}'
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# concatenate the probes together to make one big register,
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# but do so such that the first probe in the config file
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# is at the least-significant position in that big register.
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#
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# this makes part-selecting out from the memory easier to
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# implement in python, and because verilog and python conventions
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# are different, we would have had to reverse it somwehere anyway
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probes_concat = list(self.probes.keys())[::-1]
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probes_concat = '{' + ', '.join(probes_concat) + '}'
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la.sub(probes_concat, "/* PROBES_CONCAT */")
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return la.get_hdl()
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@ -584,8 +592,10 @@ class LogicAnalyzerCore:
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# functions for actually using the core:
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def run(self):
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pass
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def capture(self):
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# Check state - if it's in anything other than IDLE,
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# request to stop the existing capture
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print(" -> Resetting core...")
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@ -631,71 +641,85 @@ class LogicAnalyzerCore:
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return block_mem_contents[read_pointer:] + block_mem_contents[:read_pointer]
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def part_select(self, data, width):
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top, bottom = width
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assert top >= bottom
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mask = 2 ** (top - bottom + 1) - 1
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return (data >> bottom) & mask
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def make_widths(self, config):
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# {probe0, probe1, probe2}
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# [12, 1, 3] should produce
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# [ (15, 4) (3, 3) (2,0) ]
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widths = list(config["downlink"]["probes"].values())
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# easiest to make by summing them and incrementally subtracting
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s = sum(widths)
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slices = []
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for width in widths:
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slices.append((s - 1, s - width))
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s = s - width
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assert s == 0, "Probe sizes are weird, cannot slice bits properly"
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return slices
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def export_waveform(self, config, data, path):
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extension = path.split(".")[-1]
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assert extension == "vcd", "Unrecognized waveform export format."
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def export_vcd(self, capture_data, path):
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from vcd import VCDWriter
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vcd_file = open(path, "w")
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# Use the datetime format that iVerilog uses
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# Use the same datetime format that iVerilog uses
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timestamp = datetime.now().strftime("%a %b %w %H:%M:%S %Y")
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with VCDWriter(
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vcd_file, timescale="10 ns", date=timestamp, version="manta"
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) as writer:
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# add probes to vcd file
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vcd_probes = []
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for name, width in config["downlink"]["probes"].items():
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probe = writer.register_var("manta", name, "wire", size=width)
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vcd_probes.append(probe)
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with VCDWriter(vcd_file, '10 ns', timestamp, "manta") as writer:
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# each probe has a name, width, and writer associated with it
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signals = []
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for name, width in self.probes.items():
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signal = {
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"name" : name,
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"width" : width,
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"data" : self.part_select_capture_data(capture_data, name),
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"var": writer.register_var("manta", name, "wire", size=width)
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}
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signals.append(signal)
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# add clock to vcd file
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clock = writer.register_var("manta", "clk", "wire", size=1)
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# calculate bit widths for part selecting
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widths = self.make_widths(config)
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# add the data to each probe in the vcd file
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for timestamp in range(0, 2*len(capture_data)):
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# slice data, and dump to vcd file
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for timestamp in range(2 * len(data)):
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value = data[timestamp // 2]
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# dump clock values to vcd file
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# note: this assumes logic is triggered
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# on the rising edge of the clock, @TODO fix this
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# run the clock
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writer.change(clock, timestamp, timestamp % 2 == 0)
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for probe_num, probe in enumerate(vcd_probes):
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val = self.part_select(value, widths[probe_num])
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writer.change(probe, timestamp, val)
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# add other signals
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for signal in signals:
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var = signal["var"]
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sample = signal["data"][timestamp // 2]
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writer.change(var, timestamp, sample)
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vcd_file.close()
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def export_mem(self, capture_data, path):
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with open(path, "w") as f:
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# a wee bit of cursed string formatting, but just
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# outputs each sample as binary, padded to a fixed length
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w = self.total_probe_width
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f.writelines([f'{s:0{w}b}\n' for s in capture_data])
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def export_mem_loader(self):
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pass
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def part_select_capture_data(self, capture_data, probe_name):
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"""Given the name of the probe, part-select the appropriate bits of capture data,
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and return as an integer. Accepts capture_data as an integer or a list of integers."""
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# sum up the widths of the probes below this one
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lower = 0
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for name, width in self.probes.items():
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if name == probe_name:
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break
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lower += width
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upper = lower + (self.probes[probe_name] - 1)
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# define the part select
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mask = 2 ** (upper - lower + 1) - 1
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part_select = lambda x: (x >> lower) & mask
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# apply the part_select function depending on type
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if isinstance(capture_data, int):
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return part_select(capture_data)
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elif isinstance(capture_data, list):
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for i in capture_data:
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assert isinstance(i, int), "Can only part select on integers and list of integers."
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return [part_select(sample) for sample in capture_data]
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else:
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raise ValueError("Can only part select on integers and lists of integers.")
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class BlockMemoryCore:
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def __init__(self, config, name, base_addr, interface):
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self.name = name
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