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fix nasty addressing bug in block_memory

This commit is contained in:
Fischer Moseley 2023-08-27 12:12:25 -07:00
parent f60ec0c0e3
commit 3d722d1e60
3 changed files with 9 additions and 6 deletions
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8
src/manta/block_mem_core/block_memory.v
View File

@ -75,14 +75,14 @@ module block_memory (
// throw BRAM operations into the front of the pipeline
wea <= 0;
if( (valid_i) && (addr_i >= BASE_ADDR) && (addr_i <= MAX_ADDR)) begin
wea[addr_i % N_BRAMS] <= rw_i;
addra[addr_i % N_BRAMS] <= (addr_i - BASE_ADDR) / N_BRAMS;
dina[addr_i % N_BRAMS] <= data_i;
wea[(addr_i - BASE_ADDR) % N_BRAMS] <= rw_i;
addra[(addr_i - BASE_ADDR) % N_BRAMS] <= (addr_i - BASE_ADDR) / N_BRAMS;
dina[(addr_i - BASE_ADDR) % N_BRAMS] <= data_i;
end
// pull BRAM reads from the back of the pipeline
if( (valid_pipe[2]) && (addr_pipe[2] >= BASE_ADDR) && (addr_pipe[2] <= MAX_ADDR)) begin
data_o <= douta[addr_pipe[2] % N_BRAMS];
data_o <= douta[(addr_pipe[2] - BASE_ADDR) % N_BRAMS];
end
end

2
src/manta/la_core/__init__.py
View File

@ -75,7 +75,7 @@ class LogicAnalyzerCore:
# compute base addresses
self.fsm_base_addr = self.base_addr
self.trigger_block_base_addr = self.fsm_base_addr + 6
self.trigger_block_base_addr = self.fsm_base_addr + 7
self.total_probe_width = sum(self.probes.values())
n_brams = math.ceil(self.total_probe_width / 16)

5
src/manta/la_core/logic_analyzer_controller.v
View File

@ -63,7 +63,10 @@ module logic_analyzer_controller (
write_pointer <= write_pointer + 1;
bram_we <= 1;
if(write_pointer == trigger_loc) state <= IN_POSITION;
if(write_pointer == trigger_loc) begin
if(trig) state <= CAPTURING;
else state <= IN_POSITION;
end
end
else if(state == IN_POSITION) begin