swap to zipcpu uart_rx

.gitignore

@@ -2,6 +2,12 @@
 .DS_Store
 *.vscode/
 
+# Python outputs
+venv/
+dist/
+*.egg-info
+__pycache__/
+
 # Vivado output products
 *.Xil/
 *.log
@@ -17,17 +23,9 @@ cpu_impl_netlist.v
 *.vcd
 *.out
 
-# Manta output products
-manta.v
-
-# Python Packaging output products
-dist/
-*.egg-info
-__pycache__/
-
-# Any stray lab-bc's
-lab-bc.py
-
 # Formal outputs
 test/formal_verification/*_basic
-test/formal_verification/*_cover
+test/formal_verification/*_cover
+
+# Manta output products
+manta.v

Makefile

@@ -9,29 +9,12 @@ test: auto_gen sim formal
 examples: icestick nexys_a7
 
 clean:
-	rm *.out *.vcd
-	rm **/lab-bc.py
-	rm -rf dist/
-	rm -rf src/mantaray.egg-info
-
-	rm -rf test/formal_verification/*_basic
-	rm -rf test/formal_verification/*_cover
-
-	rm -f examples/nexys_a7/*/obj/*
-	rm -f examples/nexys_a7/*/src/manta.v
-
-	rm -f examples/icestick/*/*.bin
-	rm -f examples/icestick/*/manta.v
+	@echo "Deleting everything matched by .gitignore"
+	git clean -Xdf
 
 serve_docs:
 	mkdocs serve
 
-total_loc:
-	find . -type f \( -iname \*.sv -o -iname \*.v -o -iname \*.py -o -iname \*.yaml -o -iname \*.yml -o -iname \*.md \) | sed 's/.*/"&"/' | xargs  wc -l
-
-real_loc:
-	find src test -type f \( -iname \*.sv -o -iname \*.v -o -iname \*.py -o -iname \*.yaml -o -iname \*.md \) | sed 's/.*/"&"/' | xargs  wc -l
-
 # Python Operations
 python_build:
 	python3 -m build
@@ -47,7 +30,7 @@ python_lint:
 auto_gen:
 	python3 test/auto_gen/run_tests.py
 
-# Build Nexys A7 Examples
+# Build Examples
 NEXYS_A7_EXAMPLES := io_core_ether io_core_uart ps2_logic_analyzer video_sprite_ether video_sprite_uart block_mem_uart
 
 .PHONY: nexys_a7 $(NEXYS_A7_EXAMPLES)
@@ -60,7 +43,6 @@ $(NEXYS_A7_EXAMPLES):
 	mkdir -p obj; \
 	$(VIVADO) -mode batch -source ../build.tcl
 
-# Build Icestick Examples
 ICESTICK_EXAMPLES := io_core
 
 .PHONY: icestick $(ICESTICK_EXAMPLES)
@@ -136,4 +118,3 @@ uart_tx_tb:
 	iverilog -g2012 -o sim.out -y src/manta/uart_iface test/functional_sim/uart_tx_tb.sv
 	vvp sim.out
 	rm sim.out
-

examples/nexys_a7/block_mem_uart/api_example.py

@@ -11,8 +11,8 @@ for addr in range(1024):
     readback = m.my_block_memory.read(addr)
 
     if readback == number:
-        print(f"Success! Wrote and read back {number} from {addr}")
+        print(f"Success! Wrote and read back {hex(number)} from {hex(addr)}")
 
     else:
-        print(f"Failure! Wrote {number} to {addr}, but received {readback}")
+        print(f"Failure! Wrote {hex(number)} to {hex(addr)}, but received {hex(readback)}")
         exit()

src/manta/uart_iface/uart_rx.v

@@ -1,6 +1,9 @@
 `default_nettype none
 `timescale 1ns/1ps
 
+// Modified from Dan Gisselquist's rx_uart module,
+// available at https://zipcpu.com/tutorial/ex-09-uartrx.zip
+
 module uart_rx (
     input wire clk,
 
@@ -10,55 +13,50 @@ module uart_rx (
     output reg valid_o);
 
     parameter CLOCKS_PER_BAUD = 0;
+    localparam IDLE = 0;
+    localparam BIT_ZERO = 1;
+    localparam STOP_BIT = 9;
 
-    initial data_o = 0;
-    initial valid_o = 0;
+    reg	[3:0] state = IDLE;
+    reg	[15:0] baud_counter = 0;
+    reg zero_baud_counter;
+    assign zero_baud_counter = (baud_counter == 0);
 
-    reg [$clog2(CLOCKS_PER_BAUD)-1:0] baud_counter = 0;
-    reg [7:0] buffer = 0;
-    reg [3:0] bit_index = 0;
+    // 2FF Synchronizer
+    reg ck_uart = 1;
+    reg	q_uart = 1;
+    always @(posedge clk)
+        { ck_uart, q_uart } <= { q_uart, rx };
 
-    reg prev_rx = 1;
-    reg busy = 0;
-
-    always @(posedge clk) begin
-        prev_rx <= rx;
-        valid_o <= 0;
-
-        if (!busy) begin
-            if (prev_rx && !rx) begin
-                busy <= 1;
+    always @(posedge clk)
+        if (state == IDLE) begin
+            state <= IDLE;
+            baud_counter <= 0;
+            if (!ck_uart) begin
+                state <= BIT_ZERO;
+                baud_counter <= CLOCKS_PER_BAUD+CLOCKS_PER_BAUD/2-1'b1;
             end
         end
 
-        else begin
-            // run baud counter
-            baud_counter <= (baud_counter < CLOCKS_PER_BAUD-1) ? baud_counter + 1 : 0;
-
-            // sample rx in the middle of a baud period
-            if (baud_counter == (CLOCKS_PER_BAUD/2) - 2) begin
-
-                // fill buffer until end of byte on the wire
-                if(bit_index <= 8) begin
-                    buffer <= {rx, buffer[7:1]};
-                    bit_index = bit_index + 1;
-                end
-
-                else begin
-                    // reset system state
-                    busy <= 0;
-                    baud_counter <= 0;
-                    bit_index <= 0;
-
-                    // output word if stop bit received
-                    if(rx) begin
-                        data_o <= buffer;
-                        valid_o <= 1;
-                    end
-                end
+        else if (zero_baud_counter) begin
+            state <= state + 1;
+            baud_counter <= CLOCKS_PER_BAUD-1'b1;
+            if (state == STOP_BIT) begin
+                state <= IDLE;
+                baud_counter <= 0;
             end
         end
-    end
+
+        else baud_counter <= baud_counter - 1'b1;
+
+    always @(posedge clk)
+        if ( (zero_baud_counter) && (state != STOP_BIT) )
+            data_o <= {ck_uart, data_o[7:1]};
+
+    initial	valid_o = 1'b0;
+    always @(posedge clk)
+        valid_o <= ( (zero_baud_counter) && (state == STOP_BIT) );
+
 endmodule
 
 `default_nettype wire