add working l2 mac in hardware - need to fix ethertype to get scapy to play nice
This commit is contained in:
Fischer Moseley
parent
c507f795f1
commit
8e139bba3a
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@ -0,0 +1 @@
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!manta.v
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@ -33,7 +33,7 @@ module ethernet_rx (
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assign addr_o = data[31:16];
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assign wdata_o = data[15:0];
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assign rw_o = (ethertype == 4);
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assign valid_o = valid;
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assign valid_o = valid && ((ethertype == 4) || (ethertype == 2));
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endmodule
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@ -12,10 +12,13 @@ module ethernet_tx(
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input wire valid_i
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);
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reg [15:0] data_buf = 0;
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always @(posedge clk) if(~rw_i && valid_i) data_buf <= rdata_i;
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mac_tx mtx (
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.clk(clk),
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.data(rdata_i),
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.data(data_buf),
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.ethertype(16'h2),
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.start(~rw_i && valid_i),
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@ -0,0 +1,123 @@
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`default_nettype none
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`timescale 1ns/1ps
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/*
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This playback module was generated with Manta v0.0.0 on 24 Apr 2023 at 22:17:57 by fischerm
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If this breaks or if you've got dank formal verification memes, contact fischerm [at] mit.edu
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Provided under a GNU GPLv3 license. Go wild.
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Here's an example instantiation of the Manta module you configured, feel free to copy-paste
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this into your source!
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manta manta_inst (
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.clk(clk),
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.rx(rx),
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.tx(tx));
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*/
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module manta(
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input wire clk,
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input wire crsdv,
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input wire [1:0] rxd,
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output reg txen,
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output reg [1:0] txd);
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ethernet_rx erx (
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.clk(clk),
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.crsdv(crsdv),
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.rxd(rxd),
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.addr_o(brx_my_lut_ram_addr),
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.wdata_o(brx_my_lut_ram_wdata),
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.rw_o(brx_my_lut_ram_rw),
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.valid_o(brx_my_lut_ram_valid));
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reg [15:0] brx_my_lut_ram_addr;
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reg [15:0] brx_my_lut_ram_wdata;
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reg brx_my_lut_ram_rw;
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reg brx_my_lut_ram_valid;
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lut_ram #(.DEPTH(64)) my_lut_ram (
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.clk(clk),
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.addr_i(brx_my_lut_ram_addr),
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.wdata_i(brx_my_lut_ram_wdata),
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.rdata_i(),
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.rw_i(brx_my_lut_ram_rw),
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.valid_i(brx_my_lut_ram_valid),
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.addr_o(),
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.wdata_o(),
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.rdata_o(my_lut_ram_btx_rdata),
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.rw_o(my_lut_ram_btx_rw),
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.valid_o(my_lut_ram_btx_valid));
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reg [15:0] my_lut_ram_btx_rdata;
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reg my_lut_ram_btx_rw;
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reg my_lut_ram_btx_valid;
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ethernet_tx etx (
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.clk(clk),
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.txen(txen),
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.txd(txd),
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.rdata_i(my_lut_ram_btx_rdata),
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.rw_i(my_lut_ram_btx_rw),
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.valid_i(my_lut_ram_btx_valid));
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endmodule
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module lut_ram (
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input wire clk,
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// input port
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input wire [15:0] addr_i,
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input wire [15:0] wdata_i,
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input wire [15:0] rdata_i,
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input wire rw_i,
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input wire valid_i,
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// output port
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output reg [15:0] addr_o,
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output reg [15:0] wdata_o,
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output reg [15:0] rdata_o,
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output reg rw_o,
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output reg valid_o);
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parameter DEPTH = 8;
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parameter BASE_ADDR = 0;
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parameter READ_ONLY = 0;
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reg [DEPTH-1:0] mem [15:0];
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always @(posedge clk) begin
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addr_o <= addr_i;
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wdata_o <= wdata_i;
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rdata_o <= rdata_i;
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rw_o <= rw_i;
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valid_o <= valid_i;
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rdata_o <= rdata_i;
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if(valid_i) begin
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// check if address is valid
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if( (addr_i >= BASE_ADDR) && (addr_i <= BASE_ADDR + DEPTH - 1) ) begin
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// read/write
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if (rw_i && !READ_ONLY) mem[addr_i - BASE_ADDR] <= wdata_i;
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else rdata_o <= mem[addr_i - BASE_ADDR];
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end
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end
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end
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endmodule
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`default_nettype wire
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@ -0,0 +1,85 @@
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module ssd(
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input wire clk_in,
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input wire rst_in,
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input wire [31:0] val_in,
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output reg[6:0] cat_out,
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output reg[7:0] an_out);
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parameter COUNT_TO = 100000;
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logic[7:0] segment_state;
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logic[31:0] segment_counter;
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logic [3:0] routed_vals;
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logic [6:0] led_out;
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bto7s mbto7s (.x_in(routed_vals), .s_out(led_out));
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assign cat_out = ~led_out;
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assign an_out = ~segment_state;
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always @(*) begin
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case(segment_state)
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8'b0000_0001: routed_vals = val_in[3:0];
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8'b0000_0010: routed_vals = val_in[7:4];
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8'b0000_0100: routed_vals = val_in[11:8];
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8'b0000_1000: routed_vals = val_in[15:12];
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8'b0001_0000: routed_vals = val_in[19:16];
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8'b0010_0000: routed_vals = val_in[23:20];
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8'b0100_0000: routed_vals = val_in[27:24];
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8'b1000_0000: routed_vals = val_in[31:28];
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default: routed_vals = val_in[3:0];
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endcase
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end
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always @(posedge clk_in) begin
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if (rst_in) begin
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segment_state <= 8'b0000_0001;
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segment_counter <= 32'b0;
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end
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else begin
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if (segment_counter == COUNT_TO) begin
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segment_counter <= 32'd0;
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segment_state <= {segment_state[6:0],segment_state[7]};
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end else begin
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segment_counter <= segment_counter +1;
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end
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end
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end
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endmodule
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module bto7s(
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input wire [3:0] x_in,
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output reg [6:0] s_out);
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reg sa, sb, sc, sd, se, sf, sg;
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assign s_out = {sg, sf, se, sd, sc, sb, sa};
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// array of bits that are "one hot" with numbers 0 through 15
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reg [15:0] num;
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assign num[0] = ~x_in[3] && ~x_in[2] && ~x_in[1] && ~x_in[0];
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assign num[1] = ~x_in[3] && ~x_in[2] && ~x_in[1] && x_in[0];
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assign num[2] = x_in == 4'd2;
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assign num[3] = x_in == 4'd3;
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assign num[4] = x_in == 4'd4;
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assign num[5] = x_in == 4'd5;
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assign num[6] = x_in == 4'd6;
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assign num[7] = x_in == 4'd7;
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assign num[8] = x_in == 4'd8;
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assign num[9] = x_in == 4'd9;
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assign num[10] = x_in == 4'd10;
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assign num[11] = x_in == 4'd11;
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assign num[12] = x_in == 4'd12;
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assign num[13] = x_in == 4'd13;
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assign num[14] = x_in == 4'd14;
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assign num[15] = x_in == 4'd15;
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assign sa = num[0] || num[2] || num[3] || num[5] || num[6] || num[7] || num[8] || num[9] || num[10] || num[12] ||num[14] ||num[15];
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assign sb = num[0] || num[1] || num[2] || num[3] || num[4] || num[7] || num[8] || num[9] || num[10] || num[13];
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assign sc = num[0] || num[1] || num[3] || num[4] || num[5] || num[6] || num[7] || num[8] || num[9] || num[10] || num[11] || num[13];
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assign sd = num[0] || num[2] || num[3] || num[5] || num[6] || num[8] || num[9] || num[11] || num[12] || num[13] || num[14];
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assign se = num[0] || num[2] || num[6] || num[8] || num[10] || num[11] || num[12] || num[13] || num[14] || num[15];
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assign sf = num[0] || num[4] || num[5] || num[6] || num[8] || num[9] || num[10] || num[11] || num[12] || num[14] || num[15];
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assign sg = num[2] || num[3] || num[4] || num[5] || num[6] || num[8] || num[9] || num[10] || num[11] || num[13] || num[14] ||num[15];
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endmodule
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@ -8,6 +8,13 @@ module top_level (
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input wire [15:0] sw,
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output logic [15:0] led,
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output logic ca, cb, cc, cd, ce, cf, cg,
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output logic [7:0] an,
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output logic led16_r,
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output logic led17_r,
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output reg eth_refclk,
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output reg eth_rstn,
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@ -27,6 +34,19 @@ module top_level (
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assign eth_refclk = clk_50mhz;
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divider d (.clk(clk), .ethclk(clk_50mhz));
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assign led = manta_inst.brx_my_lut_ram_addr;
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assign led16_r = manta_inst.brx_my_lut_ram_rw;
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assign led17_r = manta_inst.brx_my_lut_ram_valid;
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logic [6:0] cat;
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assign {cg,cf,ce,cd,cc,cb,ca} = cat;
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ssd ssd (
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.clk_in(clk_50mhz),
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.rst_in(btnc),
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.val_in( {manta_inst.my_lut_ram_btx_rdata, manta_inst.brx_my_lut_ram_wdata} ),
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.cat_out(cat),
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.an_out(an));
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manta manta_inst (
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.clk(clk_50mhz),
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@ -37,51 +37,51 @@ set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[15]
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## LEDs
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# set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0]
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# set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1]
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# set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2]
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# set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3]
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# set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4]
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# set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5]
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# set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6]
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# set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7]
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# set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8]
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# set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9]
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# set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10]
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# set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11]
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# set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12]
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# set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13]
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# set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14]
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# set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15]
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set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0]
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set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1]
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set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2]
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set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3]
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set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4]
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set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5]
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set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6]
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set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7]
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set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8]
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set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9]
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set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10]
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set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11]
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set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12]
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set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13]
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set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14]
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set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15]
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# set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { led16_b }]; #IO_L5P_T0_D06_14 Sch=led16_b
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# set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { led16_g }]; #IO_L10P_T1_D14_14 Sch=led16_g
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# set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led16_r }]; #IO_L11P_T1_SRCC_14 Sch=led16_r
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set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led16_r }]; #IO_L11P_T1_SRCC_14 Sch=led16_r
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# set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led17_b }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b
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# set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { led17_g }]; #IO_0_14 Sch=led17_g
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# set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led17_r }]; #IO_L11N_T1_SRCC_14 Sch=led17_r
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set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led17_r }]; #IO_L11N_T1_SRCC_14 Sch=led17_r
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##7 segment display
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# set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca
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# set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb
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# set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc
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# set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd
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# set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce
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# set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf
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# set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg
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set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca
|
||||
set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb
|
||||
set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc
|
||||
set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd
|
||||
set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce
|
||||
set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf
|
||||
set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg
|
||||
|
||||
# set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp
|
||||
|
||||
# set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
|
||||
# set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
|
||||
# set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
|
||||
# set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
|
||||
# set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
|
||||
# set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
|
||||
# set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6]
|
||||
# set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
|
||||
set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
|
||||
set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
|
||||
set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
|
||||
set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
|
||||
set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
|
||||
set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
|
||||
set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6]
|
||||
set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
|
||||
|
||||
|
||||
##Buttons
|
||||
|
|
|
|||
|
|
@ -33,7 +33,7 @@ module ethernet_rx (
|
|||
assign addr_o = data[31:16];
|
||||
assign wdata_o = data[15:0];
|
||||
assign rw_o = (ethertype == 4);
|
||||
assign valid_o = valid;
|
||||
assign valid_o = valid && ((ethertype == 4) || (ethertype == 2));
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
|
|
@ -12,10 +12,13 @@ module ethernet_tx(
|
|||
input wire valid_i
|
||||
);
|
||||
|
||||
reg [15:0] data_buf = 0;
|
||||
always @(posedge clk) if(~rw_i && valid_i) data_buf <= rdata_i;
|
||||
|
||||
mac_tx mtx (
|
||||
.clk(clk),
|
||||
|
||||
.data(rdata_i),
|
||||
.data(data_buf),
|
||||
.ethertype(16'h2),
|
||||
.start(~rw_i && valid_i),
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue