add working ethernet_tx testbench

Makefile

@@ -31,6 +31,11 @@ auto_gen:
 # Functional Simulation
 functional_sim: io_core_tb logic_analyzer_tb bit_fifo_tb bridge_rx_tb bridge_tx_tb lut_mem_tb
 
+ethernet_rx_tb:
+	iverilog -g2012 -o sim.out -y src/manta/ether_iface test/functional_sim/ethernet_rx_tb.sv
+	vvp sim.out
+	rm sim.out
+
 mac_tb:
 	iverilog -g2012 -o sim.out -y src/manta test/functional_sim/mac_tb.sv
 	vvp sim.out

src/manta/ether_iface/aggregate.v

@@ -9,7 +9,7 @@
  * nothing happens
  */
 
-`define AGR_MAX		48
+`define AGR_MAX		56
 `define AGR_SHOW	64
 
 module aggregate (
@@ -17,7 +17,7 @@ module aggregate (
 	input wire [1:0] axiid,
 	input wire axiiv,
 
-	output reg [47:0] axiod,
+	output reg [55:0] axiod,
 	output reg axiov);
 
 	/* A quick and dirty counter. As long as this is below

src/manta/ether_iface/bitorder.v

@@ -38,6 +38,8 @@ module bitorder (
 	 * we've just come out of reset?
 	 */
 	reg [1:0] state = `BO_EMPTYB;
+	initial axiov = 0;
+	initial axiod = 0;
 
 	always @(*) begin: AXIOV
 		if (state == `BO_SENDA || state == `BO_SENDB) axiov = 1'b1;

src/manta/ether_iface/cksum.v

@@ -39,6 +39,9 @@ module cksum (
 	reg crcrst;
 
 	reg [1:0] state = `CK_FRESH;
+	initial done = 0;
+	initial kill = 0;
+	initial crcrst = 0;
 
 	crc32 cksum(
 		.clk(clk),

src/manta/ether_iface/crc32.v

@@ -19,21 +19,17 @@
  * this is the ethernet checksum!!
  */
 
-module crc32(clk, rst, axiiv, axiid, axiov, axiod);
+module crc32(
+	input wire clk,
+	input wire rst,
+	input wire axiiv,
+	input wire [1:0] axiid,
 
-	/* old style i/o declaration, for clarity.
-	 * easier on 80-char line limits...
-	 * use this if you want, we don't care
-	 */
-	input logic clk, rst;
-
-	input logic axiiv;
-	input logic[1:0] axiid;
-
-	output logic axiov;
-	output logic[31:0] axiod;
+	output reg axiov,
+	output reg [31:0] axiod);
 
 	logic[31:0] caxiod, saxiod;
+	initial caxiod = 32'hFFFF_FFFF;
 	integer i;
 
 	assign axiov = 1;

src/manta/ether_iface/ethernet_rx.v

@@ -16,7 +16,7 @@ module ethernet_rx (
     parameter FPGA_MAC = 0;
     parameter ETHERTYPE = 0;
 
-    reg [39:0] payload;
+    reg [55:0] payload;
     reg valid;
 
     mac_rx #(

src/manta/ether_iface/mac_rx.v

@@ -7,7 +7,7 @@ module mac_rx (
     input wire crsdv,
     input wire [1:0] rxd,
 
-    output reg [39:0] payload,
+    output reg [55:0] payload,
     output reg valid);
 
     parameter FPGA_MAC = 0;
@@ -46,7 +46,7 @@ module mac_rx (
         .axiov(firewall_axiov),
         .axiod(firewall_axiod));
 
-	reg [47:0] aggregate_axiod;
+	reg [55:0] aggregate_axiod;
 	reg aggregate_axiov;
 
 	aggregate a (
@@ -86,7 +86,7 @@ module mac_rx (
         else if(state == WAIT_FOR_DATA) begin
             if(aggregate_axiov) begin
                 state <= WAIT_FOR_FCS;
-                payload <= aggregate_axiod[31:0];
+                payload <= aggregate_axiod;
             end
 
             // if aggregate never gives us data,

test/functional_sim/ethernet_rx_tb.sv

@@ -0,0 +1,98 @@
+`default_nettype none
+`timescale 1ns/1ps
+
+`define FPGA_MAC 48'h69_69_5A_06_54_91
+`define HOST_MAC 48'h00_E0_4C_68_1E_0C
+`define ETHERTYPE 16'h88_B5
+
+module ethernet_rx_tb();
+
+    // https://www.youtube.com/watch?v=K35qOTQLNpA
+    logic clk;
+
+    always begin
+        #5;
+        clk = !clk;
+    end
+
+    logic crsdv;
+    logic [1:0] rxd;
+
+    logic txen;
+    logic [1:0] txd;
+
+    logic [39:0] mtx_payload;
+    logic mtx_start;
+
+    mac_tx #(
+        .SRC_MAC(`HOST_MAC),
+        .DST_MAC(`FPGA_MAC),
+        .ETHERTYPE(`ETHERTYPE),
+        .PAYLOAD_LENGTH_BYTES(5)
+    ) mtx (
+        .clk(clk),
+
+        .payload(mtx_payload),
+        .start(mtx_start),
+
+        .txen(txen),
+        .txd(txd));
+
+    assign rxd = txd;
+    assign crsdv = txen;
+
+    logic [15:0] erx_addr;
+    logic [15:0] erx_wdata;
+    logic erx_rw;
+    logic erx_valid;
+
+    ethernet_rx #(
+        .FPGA_MAC(`FPGA_MAC),
+        .ETHERTYPE(`ETHERTYPE)
+    ) erx (
+        .clk(clk),
+
+        .crsdv(crsdv),
+        .rxd(rxd),
+
+        .addr_o(erx_addr),
+        .wdata_o(erx_wdata),
+        .rw_o(erx_rw),
+        .valid_o(erx_valid));
+
+    initial begin
+        $dumpfile("ethernet_rx_tb.vcd");
+        $dumpvars(0, ethernet_rx_tb);
+        clk = 0;
+        mtx_payload = 0;
+        mtx_start = 0;
+        #50;
+
+        // try to send a read request to the bus:
+        mtx_payload = 40'h01_0002_0001;
+        mtx_start = 1;
+        #10;
+        mtx_start = 0;
+        #10000;
+
+
+
+
+        // for (int i=0; i<32; i=i+1) begin
+        //     mtx_payload = i;
+        //     mtx_start = 0;
+        //     #10;
+        //     mtx_start = 1;
+        //     #10;
+        //     mtx_start = 0;
+        //     while(!mrx_valid) #10;
+
+        //     #1000;
+
+        //     assert(mrx_payload == i) else $error("data mismatch!");
+        // end
+        $finish();
+    end
+
+endmodule
+`default_nettype wire