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flip i and j, and see the light

This commit is contained in:
Fischer Moseley 2023-04-28 00:20:27 -04:00
parent 15aa5f469f
commit cef5e9318b
2 changed files with 2 additions and 2 deletions
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2
Makefile
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@ -86,7 +86,7 @@ bridge_tx_tb:
rm sim.out
lut_mem_tb:
iverilog -g2012 -o sim.out -y src/manta test/functional_sim/lut_mem_tb.sv
iverilog -g2012 -o sim.out -y src/manta/lut_mem_core test/functional_sim/lut_mem_tb.sv
vvp sim.out
rm sim.out

2
src/manta/lut_mem_core/lut_mem.v
View File

@ -21,7 +21,7 @@ module lut_mem (
parameter DEPTH = 8;
parameter BASE_ADDR = 0;
parameter READ_ONLY = 0;
reg [DEPTH-1:0] mem [15:0];
reg [15:0] mem [DEPTH-1:0];
always @(posedge clk) begin
addr_o <= addr_i;