add bridge_rx formal to makefile
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Makefile
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Makefile
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@ -95,6 +95,7 @@ lut_mem_tb:
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# Formal Verification
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formal:
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sby -f test/formal_verification/uart_rx.sby
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sby -f test/formal_verification/bridge_rx.sby
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# Build Examples
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nexys_a7: nexys_a7_video_sprite_uart nexys_a7_io_core nexys_a7_ps2_logic_analyzer nexys_a7_lut_mem
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@ -121,38 +121,27 @@ module bridge_rx (
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`ifdef FORMAL
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always @(posedge clk) begin
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// covers
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// find_any_write_transaction: cover(rw_o == 1);
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// find_any_read_transaction: cover(rw_o == 0);
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find_any_write_transaction: cover(rw_o == 1);
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find_any_read_transaction: cover(rw_o == 0);
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// find_specific_write_transaction:
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// cover(data_o == 16'h1234 && addr_o == 16'h5678 && rw_o == 1 && valid_o == 1);
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find_specific_write_transaction:
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cover(data_o == 16'h1234 && addr_o == 16'h5678 && rw_o == 1 && valid_o == 1);
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// find_specific_read_transaction:
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// cover(addr_o == 16'h1234 && rw_o == 0 && valid_o == 1);
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find_specific_read_transaction:
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cover(addr_o == 16'h1234 && rw_o == 0 && valid_o == 1);
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// find_spacey_write_transaction:
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// cover((rw_o == 1) && ($past(valid_i, 3) == 0));
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// // asserts
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// no_back_to_back_transactions:
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// assert( ~(valid_o && $past(valid_o)) );
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// no_invalid_states:
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// assert(state == IDLE || state == READ || state == WRITE);
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// byte_counter_only_increases:
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// assert(byte_num == $past(byte_num) || byte_num == $past(byte_num) + 1 || byte_num == 0);
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// only_r_triggers_reads:
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// assert property ( (state == READ) |=> ($past(valid_i) ) );
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// state transitions
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enter_read:
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assert( ($past(state) == IDLE && state == READ) )
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find_spacey_write_transaction:
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cover((rw_o == 1) && ($past(valid_i, 3) == 0));
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// asserts
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no_back_to_back_transactions:
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assert( ~(valid_o && $past(valid_o)) );
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no_invalid_states:
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assert(state == IDLE || state == READ || state == WRITE);
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byte_counter_only_increases:
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assert(byte_num == $past(byte_num) || byte_num == $past(byte_num) + 1 || byte_num == 0);
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end
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`endif // FORMAL
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endmodule
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