add warnings for unrecognized parameters in configuration
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@ -109,6 +109,11 @@ class VerilogManipulator:
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class UARTInterface:
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def __init__(self, config):
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# Warn if unrecognized options have been given
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for option in config:
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if option not in ["port", "clock_freq", "baudrate", "chunk_size", "verbose"]:
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print(f"Warning: Ignoring unrecognized option '{option}' in UART interface.")
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# Obtain port. Try to automatically detect port if "auto" is specified
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assert "port" in config, "No serial port provided to UART core."
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self.port = config["port"]
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@ -131,15 +136,14 @@ class UARTInterface:
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# Confirm we can match baudrate suffeciently well
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actual_baudrate = self.clock_freq / clocks_per_baud
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baudrate_error = 100 * abs(actual_baudrate - self.baudrate) / self.baudrate
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assert (
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baudrate_error <= 5
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), "Unable to match target baudrate - they differ by {baudrate_error}%"
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assert baudrate_error <= 5, \
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"Unable to match target baudrate - they differ by {baudrate_error}%"
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# Set chunk_size, which is the max amount of bytes that get dumped
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# to the OS driver at a time
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self.chunk_size = 256
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if "chunk size" in config:
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self.chunk_size = config["chunk size"]
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if "chunk_size" in config:
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self.chunk_size = config["chunk_size"]
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# Set verbosity
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self.verbose = False
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@ -315,6 +319,11 @@ class IOCore:
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self.base_addr = base_addr
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self.interface = interface
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# Warn if unrecognized options have been given
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for option in config:
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if option not in ["type", "inputs", "outputs"]:
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print(f"Warning: Ignoring unrecognized option '{option}' in IO core '{self.name}'")
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# make sure we have ports defined
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assert ('inputs' in config) or ('outputs' in config), "No input or output ports specified."
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@ -426,6 +435,11 @@ class LUTRAMCore:
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self.base_addr = base_addr
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self.interface = interface
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# Warn if unrecognized options have been given
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for option in config:
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if option not in ["type", "size"]:
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print(f"Warning: Ignoring unrecognized option '{option}' in LUT Memory '{self.name}'")
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assert "size" in config, "Size not specified for LUT RAM core."
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assert config["size"] > 0, "LUT RAM must have positive size."
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assert isinstance(config["size"], int), "LUT RAM must have integer size."
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@ -458,11 +472,19 @@ class LogicAnalyzerCore:
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self.base_addr = base_addr
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self.interface = interface
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# load config
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assert (
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"sample_depth" in config
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), "Sample depth not found for logic analyzer core."
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assert isinstance(config["sample_depth"], int), "Sample depth must be an integer."
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# Warn if unrecognized options have been given
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valid_options = ["type", "sample_depth", "probes", "triggers", "trigger_location", "trigger_mode"]
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for option in config:
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if option not in valid_options:
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print(f"Warning: Ignoring unrecognized option '{option}' in Logic Analyzer core '{self.name}'")
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# Load sample depth
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assert "sample_depth" in config, \
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"Sample depth not found for Logic Analyzer core {self.name}."
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assert isinstance(config["sample_depth"], int), \
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"Sample depth must be an integer."
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self.sample_depth = config["sample_depth"]
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# Add probes
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@ -481,11 +503,17 @@ class LogicAnalyzerCore:
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# Add trigger location
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self.trigger_loc = self.sample_depth // 2
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if "trigger_loc" in config:
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assert isinstance(config["trigger_loc"], int), "Trigger location must be an integer."
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assert config["trigger_loc"] >= 0, "Trigger location cannot be negative."
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assert config["trigger_loc"] <= self.sample_depth, "Trigger location cannot exceed sample depth."
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self.trigger_loc = config["trigger_loc"]
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if "trigger_location" in config:
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assert isinstance(config["trigger_location"], int), \
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"Trigger location must be an integer."
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assert config["trigger_location"] >= 0, \
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"Trigger location cannot be negative."
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assert config["trigger_location"] <= self.sample_depth, \
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"Trigger location cannot exceed sample depth."
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self.trigger_loc = config["trigger_location"]
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# Add trigger mode
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self.SINGLE_SHOT = 0
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@ -884,6 +912,11 @@ class BlockMemoryCore:
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self.base_addr = base_addr
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self.interface = interface
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# Warn if unrecognized options have been given
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for option in config:
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if option not in ["type", "depth", "width", "expose_port"]:
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print(f"Warning: Ignoring unrecognized option '{option}' in Block Memory core '{self.name}'")
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# Determine if we expose the BRAM's second port to the top of the module
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if "expose_port" in config:
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assert isinstance(config["expose_port"], bool), "Configuring BRAM exposure must be done with a boolean."
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@ -939,7 +972,6 @@ class BlockMemoryCore:
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return self.interface.write_register(addr + self.base_addr, data)
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class Manta:
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def __init__(self, config_filepath):
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config = self.read_config_file(config_filepath)
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