remove lut_mem, clean up examples
This commit is contained in:
Fischer Moseley
parent
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40
Makefile
40
Makefile
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@ -42,7 +42,7 @@ auto_gen:
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python3 test/auto_gen/run_tests.py
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# Functional Simulation
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sim: ethernet_tx_tb ethernet_rx_tb mac_tb block_memory_tb io_core_tb logic_analyzer_tb bridge_rx_tb bridge_tx_tb lut_mem_tb block_memory_tb
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sim: ethernet_tx_tb ethernet_rx_tb mac_tb block_memory_tb io_core_tb logic_analyzer_tb bridge_rx_tb bridge_tx_tb block_memory_tb
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ethernet_tx_tb:
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iverilog -g2012 -o sim.out -y src/manta/ether_iface test/functional_sim/ethernet_tx_tb.sv
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@ -88,45 +88,26 @@ bridge_tx_tb:
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vvp sim.out
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rm sim.out
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lut_mem_tb:
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iverilog -g2012 -o sim.out -y src/manta/lut_mem_core test/functional_sim/lut_mem_tb.sv
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vvp sim.out
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rm sim.out
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# Formal Verification
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formal:
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sby -f test/formal_verification/uart_rx.sby
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sby -f test/formal_verification/bridge_rx.sby
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# Build Examples
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nexys_a7: nexys_a7_io_core_ether nexys_a7_io_core_uart nexys_a7_lut_mem_ether nexys_a7_lut_mem_uart nexys_a7_ps2_logic_analyzer nexys_a7_video_sprite_ether nexys_a7_video_sprite_uart
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nexys_a7: nexys_a7_io_core_ether nexys_a7_io_core_uart nexys_a7_ps2_logic_analyzer nexys_a7_video_sprite_ether nexys_a7_video_sprite_uart
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nexys_a7_io_core_ether:
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cd examples/nexys_a7/io_core_ether/;\
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manta gen manta.yaml src/manta.v; \
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wget https://fpga.mit.edu/6205/_static/F22/documentation/vivado/lab-bc.py; \
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wget -nc https://fpga.mit.edu/6205/_static/F22/documentation/vivado/lab-bc.py; \
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mkdir -p obj; \
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python3 lab-bc.py
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nexys_a7_io_core_uart:
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cd examples/nexys_a7/io_core_uart/; \
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manta gen manta.yaml src/manta.v; \
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wget https://fpga.mit.edu/6205/_static/F22/documentation/vivado/lab-bc.py; \
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mkdir -p obj; \
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python3 lab-bc.py
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nexys_a7_lut_mem_ether:
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cd examples/nexys_a7/lut_mem_ether/;\
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manta gen manta.yaml src/manta.v; \
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wget https://fpga.mit.edu/6205/_static/F22/documentation/vivado/lab-bc.py; \
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mkdir -p obj; \
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python3 lab-bc.py
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nexys_a7_lut_mem_uart:
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cd examples/nexys_a7/lut_mem_uart/;\
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manta gen manta.yaml src/manta.v; \
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wget https://fpga.mit.edu/6205/_static/F22/documentation/vivado/lab-bc.py; \
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wget -nc https://fpga.mit.edu/6205/_static/F22/documentation/vivado/lab-bc.py; \
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mkdir -p obj; \
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python3 lab-bc.py
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@ -134,32 +115,27 @@ nexys_a7_ps2_logic_analyzer:
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cd examples/nexys_a7/ps2_logic_analyzer/; \
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manta gen manta.yaml src/manta.v; \
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manta playback manta.yaml my_logic_analyzer sim/playback.v; \
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wget https://fpga.mit.edu/6205/_static/F22/documentation/vivado/lab-bc.py; \
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wget -nc https://fpga.mit.edu/6205/_static/F22/documentation/vivado/lab-bc.py; \
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mkdir -p obj; \
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python3 lab-bc.py
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nexys_a7_video_sprite_ether:
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cd examples/nexys_a7/video_sprite_ether;\
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manta gen manta.yaml src/manta.v; \
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wget https://fpga.mit.edu/6205/_static/F22/documentation/vivado/lab-bc.py; \
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wget -nc https://fpga.mit.edu/6205/_static/F22/documentation/vivado/lab-bc.py; \
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mkdir -p obj; \
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python3 lab-bc.py
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nexys_a7_video_sprite_uart:
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cd examples/nexys_a7/video_sprite_uart; \
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manta gen manta.yaml src/manta.v; \
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wget https://fpga.mit.edu/6205/_static/F22/documentation/vivado/lab-bc.py; \
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wget -nc https://fpga.mit.edu/6205/_static/F22/documentation/vivado/lab-bc.py; \
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mkdir -p obj; \
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python3 lab-bc.py
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icestick: icestick_io_core icestick_lut_mem
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icestick: icestick_io_core
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icestick_io_core:
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cd examples/icestick/io_core/; \
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manta gen manta.yaml manta.v; \
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./build.sh
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icestick_lut_mem:
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cd examples/icestick/lut_mem/; \
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manta gen manta.yaml manta.v; \
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./build.sh
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@ -1,29 +0,0 @@
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A LUT Memory Core is simply just a set of registers that live on the bus, and thus implemented in Look Up Tables (LUTs). Their only connection is to the bus, so they aren't reachable from user code. For bus-tied memory that's interfaceable with user code, consider the [Block Memory Core](../block_memory_core).
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LUT Memory Cores are convenient for when the host machine needs to store a small amount of data on the FPGA, accessible only to itself.
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I have no idea under what circumstances this would be useful, but perhaps someone with fresher eyes then mine would be able to see something. @Joe, thoughts?
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## Configuration
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Just like every core, a given LUT Memory core is described in Manta's configuration file:
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```yaml
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cores:
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my_lut_mem:
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type: lut_mem
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size: 64
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```
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Each register is 16-bits wide, so the only configuration option is just the size of the memory.
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## Python
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The core can be written to and read from in Python with the following:
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```python
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m.my_lut_mem.write(addr, data)
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foo = m.my_lut_mem.read(addr)
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```
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## Examples
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A LUT Memory core is used in the lut_mem examples, for both the [nexys_a7](https://github.com/fischermoseley/manta/tree/main/examples/nexys_a7/lut_mem_uart) and the [icestick](https://github.com/fischermoseley/manta/tree/main/examples/icestick/lut_mem).
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@ -1,6 +0,0 @@
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#!/bin/bash
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yosys -p 'synth_ice40 -top top_level -json top_level.json' top_level.sv
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nextpnr-ice40 --hx1k --json top_level.json --pcf top_level.pcf --asc top_level.asc
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icepack top_level.asc top_level.bin
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rm -f *.json
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rm -f *.asc
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@ -1 +0,0 @@
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../common/build.sh
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@ -0,0 +1,6 @@
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#!/bin/bash
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yosys -p 'synth_ice40 -top top_level -json top_level.json' top_level.sv
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nextpnr-ice40 --hx1k --json top_level.json --pcf top_level.pcf --asc top_level.asc
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icepack top_level.asc top_level.bin
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rm -f *.json
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rm -f *.asc
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@ -1 +0,0 @@
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../common/build.sh
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@ -1,10 +0,0 @@
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---
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cores:
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my_lut_mem:
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type: lut_mem
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size: 64
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uart:
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port: "auto"
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baudrate: 115200
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clock_freq: 100000000
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@ -1,12 +0,0 @@
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from manta import Manta
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from random import randint
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m = Manta('manta.yaml')
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for addr in range(m.my_lut_mem.size):
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write_data = randint(0, (2**16)-1)
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m.my_lut_mem.write(addr, write_data)
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read_data = m.my_lut_mem.read(addr)
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print(f"test addr: {addr} with data: {write_data}")
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print(f" -> correct data received on readback?: {write_data == read_data}")
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@ -1,67 +0,0 @@
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# Generic iCEstick placement constraints file
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# Red LEDs
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#set_io LED0 99
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#set_io LED1 98
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#set_io LED2 97
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#set_io LED3 96
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# Green LED
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#set_io LED4 95
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# IrDA port
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#set_io RXD 106
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#set_io TXD 105
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#set_io SD 107
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# Pmod connector
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#set_io PIO1_02 78 # Pin 1
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#set_io PIO1_03 79 # Pin 2
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#set_io PIO1_04 80 # Pin 3
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#set_io PIO1_05 81 # Pin 4
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#set_io PIO1_06 87 # Pin 7
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#set_io PIO1_07 88 # Pin 8
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#set_io PIO1_08 90 # Pin 9
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#set_io PIO1_09 91 # Pin 10
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# Connector J1
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#set_io PIO0_02 112 # Pin 3
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#set_io PIO0_03 113 # Pin 4
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#set_io PIO0_04 114 # Pin 5
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#set_io PIO0_05 115 # Pin 6
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#set_io PIO0_06 116 # Pin 7
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#set_io PIO0_07 117 # Pin 8
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#set_io PIO0_08 118 # Pin 9
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#set_io PIO0_09 119 # Pin 10
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# Connector J3
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#set_io PIO2_17 62 # Pin 3
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#set_io PIO2_16 61 # Pin 4
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#set_io PIO2_15 60 # Pin 5
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#set_io PIO2_14 56 # Pin 6
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#set_io PIO2_13 48 # Pin 7
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#set_io PIO2_12 47 # Pin 8
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#set_io PIO2_11 45 # Pin 9
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#set_io PIO2_10 44 # Pin 10
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# FTDI Port B UART
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#set_io DCDn 1
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#set_io DSRn 2
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#set_io DTRn 3
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#set_io CTSn 4
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#set_io RTSn 7
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set_io rs232_tx_ttl 8
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set_io rs232_rx_ttl 9
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# SPI
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#set_io SPI_SCK 70
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#set_io SPI_SI 68
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#set_io SPI_SO 67
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#set_io SPI_SS_B 71
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# Configuration pins
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#set_io CDONE 65
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#set_io CRESET_B 66
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# 12 MHz clock
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set_io clk 21
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@ -1,20 +0,0 @@
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`default_nettype none
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`timescale 1ns / 1ps
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`include "manta.v"
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module top_level (
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input wire clk,
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input wire rs232_rx_ttl,
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output logic rs232_tx_ttl
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);
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manta manta_inst (
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.clk(clk),
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.rx(rs232_rx_ttl),
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.tx(rs232_tx_ttl));
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endmodule
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`default_nettype wire
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@ -1,68 +0,0 @@
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#!/usr/bin/tclsh
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# jay's build script
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# pass -tclargs -d to generate diagnostics
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# switches
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set partNum xc7a100tcsg324-1
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set outputDir output_files
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set verbose 0
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if { $argc > 0 } {
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if { $argc == 1 && [string compare [ lindex $argv 0 ] "-d"] == 0 } {
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set verbose 1
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} else {
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puts "usage: $argv0 \[-d\]"
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exit 1
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}
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}
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file mkdir $outputDir
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set files [glob -nocomplain "$outputDir/*"]
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if {[llength $files] != 0} {
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file delete -force {*}[glob -directory $outputDir *];
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}
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read_verilog -sv [ glob ./src/*.{sv,v,svh,vh} ]
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read_xdc ./xdc/top_level.xdc
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set_part $partNum
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# synth
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synth_design -top top_level -part $partNum -verbose
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report_utilization -file $outputDir/post_synth_util.rpt
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if { $verbose } {
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report_timing_summary -file $outputDir/post_synth_timing_summary.rpt
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report_timing -file $outputDir/post_synth_timing.rpt
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}
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# place
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opt_design
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place_design
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phys_opt_design
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report_utilization -file $outputDir/post_place_util.rpt
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if { $verbose } {
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report_clock_utilization -file $outputDir/clock_util.rpt
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report_timing_summary -file $outputDir/post_place_timing_summary.rpt
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report_timing -file $outputDir/post_place_timing.rpt
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}
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# route design and generate bitstream
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route_design -directive Explore
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write_bitstream -force $outputDir/final.bit
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if { $verbose } {
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report_route_status -file $outputDir/post_route_status.rpt
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report_timing_summary -file $outputDir/post_route_timing_summary.rpt
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report_timing -file $outputDir/post_route_timing.rpt
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report_power -file $outputDir/post_route_power.rpt
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report_drc -file $outputDir/post_imp_drc.rpt
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write_verilog -force $outputDir/cpu_impl_netlist.v -mode timesim -sdf_anno true
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# unfortunately, does nothing
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show_schematic [ get_cells ]
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}
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exec sh -c "rm -rf *.jou *.log"
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@ -1,73 +0,0 @@
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`default_nettype none
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`timescale 1ns/1ps
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module ssd (
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input wire clk,
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input wire [31:0] val,
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output reg [6:0] cat,
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output reg [7:0] an);
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parameter COUNT_TO = 100000;
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reg [7:0] segment_state = 8'b0000_0001;
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reg [31:0] segment_counter = 32'b0;
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reg [3:0] digit;
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reg [6:0] led_out;
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bto7s mbto7s (
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.x_in(digit),
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.s_out(led_out));
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assign cat = ~led_out;
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assign an = ~segment_state;
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always @(*) begin
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case(segment_state)
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8'b0000_0001: digit = val[3:0];
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8'b0000_0010: digit = val[7:4];
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8'b0000_0100: digit = val[11:8];
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8'b0000_1000: digit = val[15:12];
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8'b0001_0000: digit = val[19:16];
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8'b0010_0000: digit = val[23:20];
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8'b0100_0000: digit = val[27:24];
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8'b1000_0000: digit = val[31:28];
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default: digit = val[3:0];
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endcase
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end
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always @(posedge clk) begin
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segment_counter <= segment_counter + 1;
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if (segment_counter == COUNT_TO) begin
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segment_counter <= 32'd0;
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segment_state <= {segment_state[6:0], segment_state[7]};
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end
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end
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endmodule
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module bto7s (
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input wire [3:0] x_in,
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output reg [6:0] s_out);
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reg sa, sb, sc, sd, se, sf, sg;
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assign s_out = {sg, sf, se, sd, sc, sb, sa};
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// array of bits that are "one hot" with numbers 0 through 15
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reg [15:0] num;
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genvar i;
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generate
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for(i=0; i<16; i=i+1)
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assign num[i] = (x_in == i);
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endgenerate
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// map one-hot bits to active segments
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assign sa = (num & 16'b1101_0111_1110_1101) > 0;
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assign sb = (num & 16'b0010_0111_1001_1111) > 0;
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assign sc = (num & 16'b0010_1111_1111_1011) > 0;
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assign sd = (num & 16'b0111_1011_0110_1101) > 0;
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assign se = (num & 16'b1111_1101_0100_0101) > 0;
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assign sf = (num & 16'b1101_1111_0111_0001) > 0;
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assign sg = (num & 16'b1110_1111_0111_1100) > 0;
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endmodule
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`default_nettype wire
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@ -20,7 +20,6 @@ cores:
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led17_g: 1
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led17_r: 1
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uart:
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port: "auto"
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baudrate: 115200
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clock_freq: 100000000
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ethernet:
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interface: "en8"
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host_mac: "12:34:56:78:90:ab"
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@ -1,73 +0,0 @@
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`default_nettype none
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`timescale 1ns/1ps
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module ssd (
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input wire clk,
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input wire [31:0] val,
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output reg [6:0] cat,
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output reg [7:0] an);
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parameter COUNT_TO = 100000;
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reg [7:0] segment_state = 8'b0000_0001;
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reg [31:0] segment_counter = 32'b0;
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reg [3:0] digit;
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reg [6:0] led_out;
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bto7s mbto7s (
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.x_in(digit),
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.s_out(led_out));
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assign cat = ~led_out;
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assign an = ~segment_state;
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always @(*) begin
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case(segment_state)
|
||||
8'b0000_0001: digit = val[3:0];
|
||||
8'b0000_0010: digit = val[7:4];
|
||||
8'b0000_0100: digit = val[11:8];
|
||||
8'b0000_1000: digit = val[15:12];
|
||||
8'b0001_0000: digit = val[19:16];
|
||||
8'b0010_0000: digit = val[23:20];
|
||||
8'b0100_0000: digit = val[27:24];
|
||||
8'b1000_0000: digit = val[31:28];
|
||||
default: digit = val[3:0];
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
segment_counter <= segment_counter + 1;
|
||||
|
||||
if (segment_counter == COUNT_TO) begin
|
||||
segment_counter <= 32'd0;
|
||||
segment_state <= {segment_state[6:0], segment_state[7]};
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
module bto7s (
|
||||
input wire [3:0] x_in,
|
||||
output reg [6:0] s_out);
|
||||
|
||||
reg sa, sb, sc, sd, se, sf, sg;
|
||||
assign s_out = {sg, sf, se, sd, sc, sb, sa};
|
||||
|
||||
// array of bits that are "one hot" with numbers 0 through 15
|
||||
reg [15:0] num;
|
||||
genvar i;
|
||||
generate
|
||||
for(i=0; i<16; i=i+1)
|
||||
assign num[i] = (x_in == i);
|
||||
endgenerate
|
||||
|
||||
// map one-hot bits to active segments
|
||||
assign sa = (num & 16'b1101_0111_1110_1101) > 0;
|
||||
assign sb = (num & 16'b0010_0111_1001_1111) > 0;
|
||||
assign sc = (num & 16'b0010_1111_1111_1011) > 0;
|
||||
assign sd = (num & 16'b0111_1011_0110_1101) > 0;
|
||||
assign se = (num & 16'b1111_1101_0100_0101) > 0;
|
||||
assign sf = (num & 16'b1101_1111_0111_0001) > 0;
|
||||
assign sg = (num & 16'b1110_1111_0111_1100) > 0;
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
|
|
@ -3,10 +3,11 @@
|
|||
|
||||
module top_level (
|
||||
input wire clk,
|
||||
input wire cpu_resetn,
|
||||
|
||||
input wire eth_crsdv,
|
||||
input wire [1:0] eth_rxd,
|
||||
output logic [1:0] eth_txd,
|
||||
output logic eth_txen,
|
||||
output logic eth_refclk,
|
||||
output logic eth_rstn,
|
||||
|
||||
|
|
@ -15,131 +16,45 @@ module top_level (
|
|||
input wire btnl,
|
||||
input wire btnr,
|
||||
input wire btnc,
|
||||
|
||||
input wire [15:0] sw,
|
||||
|
||||
output logic [15:0] led,
|
||||
output logic led16_b,
|
||||
output logic led16_g,
|
||||
output logic led16_r,
|
||||
output logic led17_b,
|
||||
output logic led17_g,
|
||||
output logic led17_r,
|
||||
output logic led17_r);
|
||||
|
||||
|
||||
output logic ca, cb, cc, cd, ce, cf, cg,
|
||||
output logic [7:0] an,
|
||||
|
||||
input wire uart_txd_in,
|
||||
output logic uart_rxd_out);
|
||||
|
||||
logic rst;
|
||||
assign rst = ~cpu_resetn;
|
||||
|
||||
/* the ethernet clock runs at 50mhz
|
||||
* we run at 100mhz; divide the clock
|
||||
* accordingly...
|
||||
*/
|
||||
// 50MHz clock generation for the RMII
|
||||
logic ethclk;
|
||||
|
||||
/* ether -> { cksum, bitorder } */
|
||||
logic[1:0] ether_axiod;
|
||||
logic ether_axiov;
|
||||
|
||||
/* cksum -> top_level */
|
||||
logic cksum_done, cksum_kill;
|
||||
|
||||
/* bitorder -> firewall */
|
||||
logic[1:0] bitorder_axiod;
|
||||
logic bitorder_axiov;
|
||||
|
||||
/* firewall -> aggregate */
|
||||
logic[1:0] firewall_axiod;
|
||||
logic firewall_axiov;
|
||||
|
||||
/* aggregate output */
|
||||
logic[31:0] aggregate_axiod;
|
||||
logic aggregate_axiov;
|
||||
|
||||
divider div(
|
||||
divider div (
|
||||
.clk(clk),
|
||||
.ethclk(ethclk));
|
||||
|
||||
ether e(
|
||||
.clk(ethclk),
|
||||
.rst(rst),
|
||||
.rxd(eth_rxd),
|
||||
.crsdv(eth_crsdv),
|
||||
.axiov(ether_axiov),
|
||||
.axiod(ether_axiod));
|
||||
|
||||
bitorder b(
|
||||
.clk(ethclk),
|
||||
.rst(rst),
|
||||
.axiiv(ether_axiov),
|
||||
.axiid(ether_axiod),
|
||||
.axiov(bitorder_axiov),
|
||||
.axiod(bitorder_axiod));
|
||||
|
||||
firewall f(
|
||||
.clk(ethclk),
|
||||
.rst(rst),
|
||||
.axiiv(bitorder_axiov),
|
||||
.axiid(bitorder_axiod),
|
||||
.axiov(firewall_axiov),
|
||||
.axiod(firewall_axiod));
|
||||
|
||||
aggregate a(
|
||||
.clk(ethclk),
|
||||
.rst(rst),
|
||||
.axiiv(firewall_axiov),
|
||||
.axiid(firewall_axiod),
|
||||
.axiov(aggregate_axiov),
|
||||
.axiod(aggregate_axiod));
|
||||
|
||||
cksum c(
|
||||
.clk(ethclk),
|
||||
.rst(rst),
|
||||
.axiiv(ether_axiov),
|
||||
.axiid(ether_axiod),
|
||||
.done(cksum_done),
|
||||
.kill(cksum_kill));
|
||||
|
||||
assign eth_rstn = ~rst;
|
||||
assign eth_rstn = 1;
|
||||
assign eth_refclk = ethclk;
|
||||
|
||||
manta manta (
|
||||
.clk(ethclk),
|
||||
manta manta_inst (
|
||||
.clk(ethclk),
|
||||
|
||||
.rx(uart_txd_in),
|
||||
.tx(uart_rxd_out),
|
||||
.crsdv(eth_crsdv),
|
||||
.rxd(eth_rxd),
|
||||
.txen(eth_txen),
|
||||
.txd(eth_txd),
|
||||
|
||||
.brx_my_io_core_addr(aggregate_axiod[31:16]),
|
||||
.brx_my_io_core_data(aggregate_axiod[15:0]),
|
||||
.brx_my_io_core_rw(1'b1),
|
||||
.brx_my_io_core_valid(aggregate_axiov),
|
||||
|
||||
.btnu(btnu),
|
||||
.btnd(btnd),
|
||||
.btnl(btnl),
|
||||
.btnr(btnr),
|
||||
.btnc(btnc),
|
||||
.sw(sw),
|
||||
.led(led),
|
||||
.led16_b(led16_b),
|
||||
.led16_g(led16_g),
|
||||
.led16_r(led16_r),
|
||||
.led17_b(led17_b),
|
||||
.led17_g(led17_g),
|
||||
.led17_r(led17_r));
|
||||
|
||||
logic [31:0] aggregate_axiod_persistent;
|
||||
always_ff @(posedge ethclk) if (aggregate_axiov) aggregate_axiod_persistent <= aggregate_axiod;
|
||||
ssd ssd (
|
||||
.clk(ethclk),
|
||||
.val(aggregate_axiod_persistent),
|
||||
.cat({cg,cf,ce,cd,cc,cb,ca}),
|
||||
.an(an));
|
||||
.btnu(btnu),
|
||||
.btnd(btnd),
|
||||
.btnl(btnl),
|
||||
.btnr(btnr),
|
||||
.btnc(btnc),
|
||||
.sw(sw),
|
||||
.led(led),
|
||||
.led16_b(led16_b),
|
||||
.led16_g(led16_g),
|
||||
.led16_r(led16_r),
|
||||
.led17_b(led17_b),
|
||||
.led17_g(led17_g),
|
||||
.led17_r(led17_r));
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
|
|
@ -1,16 +1,10 @@
|
|||
## R1.0 2019-08-27
|
||||
## Updated by jodalyst in 2020-2022
|
||||
## all inputs/outputs changed to lowercase; arrays start with zero.
|
||||
## system clock renamed to clk
|
||||
## ja, jb, jc, jd renamed to 0-7
|
||||
## xa port renamed 0-3
|
||||
## seven segments renamed to a,b,c,d,e,f,dp
|
||||
|
||||
## This file is a general .xdc for the Nexys4 DDR Rev. C
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## This file has been modified from the default .xdc provided by Digilent for the Nexys A7
|
||||
|
||||
## Clock signal - uncomment _both_ of these lines to create clk_100mhz
|
||||
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk
|
||||
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk}];
|
||||
|
|
@ -64,29 +58,29 @@ set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led17_
|
|||
|
||||
##7 segment display
|
||||
|
||||
set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca
|
||||
set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb
|
||||
set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc
|
||||
set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd
|
||||
set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce
|
||||
set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf
|
||||
set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg
|
||||
#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca
|
||||
#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb
|
||||
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc
|
||||
#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd
|
||||
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce
|
||||
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf
|
||||
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg
|
||||
|
||||
# set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp
|
||||
|
||||
set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
|
||||
set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
|
||||
set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
|
||||
set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
|
||||
set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
|
||||
set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
|
||||
set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6]
|
||||
set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
|
||||
#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
|
||||
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
|
||||
#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
|
||||
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
|
||||
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
|
||||
#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6]
|
||||
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
|
||||
|
||||
|
||||
##Buttons
|
||||
|
||||
set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn
|
||||
#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn
|
||||
|
||||
set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btnc }]; #IO_L9P_T1_DQS_14 Sch=btnc
|
||||
set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { btnu }]; #IO_L4N_T0_D05_14 Sch=btnu
|
||||
|
|
@ -222,8 +216,8 @@ set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btnd }
|
|||
|
||||
##USB-RS232 Interface
|
||||
|
||||
set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in
|
||||
set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out
|
||||
#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in
|
||||
#set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out
|
||||
#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { uart_cts }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts
|
||||
#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { uart_rts }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts
|
||||
|
||||
|
|
@ -242,9 +236,9 @@ set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { eth_cr
|
|||
#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr
|
||||
set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0]
|
||||
set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1]
|
||||
#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { eth_txen }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen
|
||||
#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0]
|
||||
#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1]
|
||||
set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { eth_txen }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen
|
||||
set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0]
|
||||
set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1]
|
||||
set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { eth_refclk }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk
|
||||
#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { eth_intn }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn
|
||||
|
||||
|
|
|
|||
|
|
@ -1,73 +0,0 @@
|
|||
`default_nettype none
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module ssd (
|
||||
input wire clk,
|
||||
input wire [31:0] val,
|
||||
output reg [6:0] cat,
|
||||
output reg [7:0] an);
|
||||
|
||||
parameter COUNT_TO = 100000;
|
||||
|
||||
reg [7:0] segment_state = 8'b0000_0001;
|
||||
reg [31:0] segment_counter = 32'b0;
|
||||
reg [3:0] digit;
|
||||
reg [6:0] led_out;
|
||||
|
||||
bto7s mbto7s (
|
||||
.x_in(digit),
|
||||
.s_out(led_out));
|
||||
|
||||
assign cat = ~led_out;
|
||||
assign an = ~segment_state;
|
||||
|
||||
always @(*) begin
|
||||
case(segment_state)
|
||||
8'b0000_0001: digit = val[3:0];
|
||||
8'b0000_0010: digit = val[7:4];
|
||||
8'b0000_0100: digit = val[11:8];
|
||||
8'b0000_1000: digit = val[15:12];
|
||||
8'b0001_0000: digit = val[19:16];
|
||||
8'b0010_0000: digit = val[23:20];
|
||||
8'b0100_0000: digit = val[27:24];
|
||||
8'b1000_0000: digit = val[31:28];
|
||||
default: digit = val[3:0];
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
segment_counter <= segment_counter + 1;
|
||||
|
||||
if (segment_counter == COUNT_TO) begin
|
||||
segment_counter <= 32'd0;
|
||||
segment_state <= {segment_state[6:0], segment_state[7]};
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
module bto7s (
|
||||
input wire [3:0] x_in,
|
||||
output reg [6:0] s_out);
|
||||
|
||||
reg sa, sb, sc, sd, se, sf, sg;
|
||||
assign s_out = {sg, sf, se, sd, sc, sb, sa};
|
||||
|
||||
// array of bits that are "one hot" with numbers 0 through 15
|
||||
reg [15:0] num;
|
||||
genvar i;
|
||||
generate
|
||||
for(i=0; i<16; i=i+1)
|
||||
assign num[i] = (x_in == i);
|
||||
endgenerate
|
||||
|
||||
// map one-hot bits to active segments
|
||||
assign sa = (num & 16'b1101_0111_1110_1101) > 0;
|
||||
assign sb = (num & 16'b0010_0111_1001_1111) > 0;
|
||||
assign sc = (num & 16'b0010_1111_1111_1011) > 0;
|
||||
assign sd = (num & 16'b0111_1011_0110_1101) > 0;
|
||||
assign se = (num & 16'b1111_1101_0100_0101) > 0;
|
||||
assign sf = (num & 16'b1101_1111_0111_0001) > 0;
|
||||
assign sg = (num & 16'b1110_1111_0111_1100) > 0;
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
|
|
@ -3,7 +3,9 @@
|
|||
|
||||
module top_level (
|
||||
input wire clk,
|
||||
input wire cpu_resetn,
|
||||
|
||||
input wire uart_txd_in,
|
||||
output logic uart_rxd_out,
|
||||
|
||||
input wire btnu,
|
||||
input wire btnd,
|
||||
|
|
@ -14,23 +16,14 @@ module top_level (
|
|||
input wire [15:0] sw,
|
||||
|
||||
output logic [15:0] led,
|
||||
output logic dp,
|
||||
output logic led16_b,
|
||||
output logic led16_g,
|
||||
output logic led16_r,
|
||||
output logic led17_b,
|
||||
output logic led17_g,
|
||||
output logic led17_r,
|
||||
output logic led17_r);
|
||||
|
||||
|
||||
output logic ca, cb, cc, cd, ce, cf, cg,
|
||||
output logic [7:0] an,
|
||||
|
||||
input wire uart_txd_in,
|
||||
output logic uart_rxd_out
|
||||
);
|
||||
|
||||
manta manta (
|
||||
manta manta_inst (
|
||||
.clk(clk),
|
||||
|
||||
.rx(uart_txd_in),
|
||||
|
|
@ -50,27 +43,6 @@ module top_level (
|
|||
.led17_g(led17_g),
|
||||
.led17_r(led17_r));
|
||||
|
||||
// Show bus on 7-segment display
|
||||
reg [15:0] addr_latched = 0;
|
||||
reg [15:0] data_latched = 0;
|
||||
reg rw_latched = 0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (manta.brx_my_io_core_valid) begin
|
||||
addr_latched <= manta.my_io_core_brx_addr;
|
||||
data_latched <= manta.my_io_core_brx_data;
|
||||
rw_latched <= manta.my_io_core_btx_rw;
|
||||
end
|
||||
end
|
||||
|
||||
ssd ssd (
|
||||
.clk(clk),
|
||||
.val( (addr_latched << 16) | (data_latched) ),
|
||||
.cat({cg,cf,ce,cd,cc,cb,ca}),
|
||||
.an(an));
|
||||
|
||||
assign dp = rw_latched;
|
||||
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
|
|
@ -1,16 +1,10 @@
|
|||
## R1.0 2019-08-27
|
||||
## Updated by jodalyst in 2020-2022
|
||||
## all inputs/outputs changed to lowercase; arrays start with zero.
|
||||
## system clock renamed to clk
|
||||
## ja, jb, jc, jd renamed to 0-7
|
||||
## xa port renamed 0-3
|
||||
## seven segments renamed to a,b,c,d,e,f,dp
|
||||
|
||||
## This file is a general .xdc for the Nexys4 DDR Rev. C
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## This file has been modified from the default .xdc provided by Digilent for the Nexys A7
|
||||
|
||||
## Clock signal - uncomment _both_ of these lines to create clk_100mhz
|
||||
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk
|
||||
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk}];
|
||||
|
|
@ -64,29 +58,29 @@ set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led17_
|
|||
|
||||
##7 segment display
|
||||
|
||||
set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca
|
||||
set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb
|
||||
set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc
|
||||
set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd
|
||||
set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce
|
||||
set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf
|
||||
set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg
|
||||
#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca
|
||||
#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb
|
||||
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc
|
||||
#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd
|
||||
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce
|
||||
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf
|
||||
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg
|
||||
|
||||
set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp
|
||||
|
||||
set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
|
||||
set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
|
||||
set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
|
||||
set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
|
||||
set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
|
||||
set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
|
||||
set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6]
|
||||
set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
|
||||
#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
|
||||
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
|
||||
#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
|
||||
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
|
||||
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
|
||||
#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6]
|
||||
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
|
||||
|
||||
|
||||
##Buttons
|
||||
|
||||
set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn
|
||||
#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn
|
||||
|
||||
set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btnc }]; #IO_L9P_T1_DQS_14 Sch=btnc
|
||||
set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { btnu }]; #IO_L4N_T0_D05_14 Sch=btnu
|
||||
|
|
|
|||
|
|
@ -1,8 +0,0 @@
|
|||
---
|
||||
cores:
|
||||
my_lut_mem:
|
||||
type: lut_mem
|
||||
size: 64
|
||||
|
||||
ethernet:
|
||||
interface: "en8"
|
||||
|
|
@ -1,23 +0,0 @@
|
|||
from manta import Manta
|
||||
from random import randint
|
||||
|
||||
m = Manta("manta.yaml")
|
||||
|
||||
# The API supports reads/writes to single addresses:
|
||||
m.my_lut_mem.write(4, 42)
|
||||
print(m.my_lut_mem.read(4))
|
||||
|
||||
# As it does read/writes to multiple addresses at once:
|
||||
addrs = list(range(m.my_lut_mem.size))
|
||||
m.my_lut_mem.write(addrs, addrs)
|
||||
print(m.my_lut_mem.read(addrs))
|
||||
|
||||
# And here's a little test to write random data and read it back:
|
||||
for addr in range(m.my_lut_mem.size):
|
||||
write_data = randint(0, (2**16)-1)
|
||||
m.my_lut_mem.write(addr, write_data)
|
||||
|
||||
read_data = m.my_lut_mem.read(addr)
|
||||
print(f"test addr: {addr} with data: {hex(write_data)}")
|
||||
print(f" -> correct data received on readback?: {write_data == read_data}")
|
||||
assert write_data == read_data, "data read differs from data written!"
|
||||
|
|
@ -1,73 +0,0 @@
|
|||
`default_nettype none
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module ssd (
|
||||
input wire clk,
|
||||
input wire [31:0] val,
|
||||
output reg [6:0] cat,
|
||||
output reg [7:0] an);
|
||||
|
||||
parameter COUNT_TO = 100000;
|
||||
|
||||
reg [7:0] segment_state = 8'b0000_0001;
|
||||
reg [31:0] segment_counter = 32'b0;
|
||||
reg [3:0] digit;
|
||||
reg [6:0] led_out;
|
||||
|
||||
bto7s mbto7s (
|
||||
.x_in(digit),
|
||||
.s_out(led_out));
|
||||
|
||||
assign cat = ~led_out;
|
||||
assign an = ~segment_state;
|
||||
|
||||
always @(*) begin
|
||||
case(segment_state)
|
||||
8'b0000_0001: digit = val[3:0];
|
||||
8'b0000_0010: digit = val[7:4];
|
||||
8'b0000_0100: digit = val[11:8];
|
||||
8'b0000_1000: digit = val[15:12];
|
||||
8'b0001_0000: digit = val[19:16];
|
||||
8'b0010_0000: digit = val[23:20];
|
||||
8'b0100_0000: digit = val[27:24];
|
||||
8'b1000_0000: digit = val[31:28];
|
||||
default: digit = val[3:0];
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
segment_counter <= segment_counter + 1;
|
||||
|
||||
if (segment_counter == COUNT_TO) begin
|
||||
segment_counter <= 32'd0;
|
||||
segment_state <= {segment_state[6:0], segment_state[7]};
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
module bto7s (
|
||||
input wire [3:0] x_in,
|
||||
output reg [6:0] s_out);
|
||||
|
||||
reg sa, sb, sc, sd, se, sf, sg;
|
||||
assign s_out = {sg, sf, se, sd, sc, sb, sa};
|
||||
|
||||
// array of bits that are "one hot" with numbers 0 through 15
|
||||
reg [15:0] num;
|
||||
genvar i;
|
||||
generate
|
||||
for(i=0; i<16; i=i+1)
|
||||
assign num[i] = (x_in == i);
|
||||
endgenerate
|
||||
|
||||
// map one-hot bits to active segments
|
||||
assign sa = (num & 16'b1101_0111_1110_1101) > 0;
|
||||
assign sb = (num & 16'b0010_0111_1001_1111) > 0;
|
||||
assign sc = (num & 16'b0010_1111_1111_1011) > 0;
|
||||
assign sd = (num & 16'b0111_1011_0110_1101) > 0;
|
||||
assign se = (num & 16'b1111_1101_0100_0101) > 0;
|
||||
assign sf = (num & 16'b1101_1111_0111_0001) > 0;
|
||||
assign sg = (num & 16'b1110_1111_0111_1100) > 0;
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
|
|
@ -1,60 +0,0 @@
|
|||
`default_nettype none
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module top_level (
|
||||
input wire clk,
|
||||
|
||||
output logic [15:0] led,
|
||||
output logic ca, cb, cc, cd, ce, cf, cg,
|
||||
output logic dp,
|
||||
output logic [7:0] an,
|
||||
|
||||
output logic led16_r,
|
||||
output logic led17_r,
|
||||
|
||||
output reg eth_refclk,
|
||||
output reg eth_rstn,
|
||||
|
||||
input wire eth_crsdv,
|
||||
input wire [1:0] eth_rxd,
|
||||
|
||||
output reg eth_txen,
|
||||
output reg [1:0] eth_txd);
|
||||
|
||||
assign eth_rstn = 1;
|
||||
|
||||
logic clk_50mhz;
|
||||
assign eth_refclk = clk_50mhz;
|
||||
divider d (.clk(clk), .ethclk(clk_50mhz));
|
||||
|
||||
manta manta_inst (
|
||||
.clk(clk_50mhz),
|
||||
|
||||
.crsdv(eth_crsdv),
|
||||
.rxd(eth_rxd),
|
||||
.txen(eth_txen),
|
||||
.txd(eth_txd));
|
||||
|
||||
// Show bus on 7-segment display
|
||||
reg [15:0] addr_latched = 0;
|
||||
reg [15:0] data_latched = 0;
|
||||
reg rw_latched = 0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (manta_inst.brx_my_lut_mem_valid) begin
|
||||
addr_latched <= manta_inst.my_lut_mem_brx_addr;
|
||||
data_latched <= manta_inst.my_lut_mem_brx_data;
|
||||
rw_latched <= manta_inst.my_lut_mem_btx_rw;
|
||||
end
|
||||
end
|
||||
|
||||
ssd ssd (
|
||||
.clk(clk),
|
||||
.val( (addr_latched << 16) | (data_latched) ),
|
||||
.cat({cg,cf,ce,cd,cc,cb,ca}),
|
||||
.an(an));
|
||||
|
||||
assign dp = rw_latched;
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
|
|
@ -1,260 +0,0 @@
|
|||
## R1.0 2019-08-27
|
||||
## Updated by jodalyst in 2020-2022
|
||||
## all inputs/outputs changed to lowercase; arrays start with zero.
|
||||
## system clock renamed to clk
|
||||
## ja, jb, jc, jd renamed to 0-7
|
||||
## xa port renamed 0-3
|
||||
## seven segments renamed to a,b,c,d,e,f,dp
|
||||
|
||||
## This file is a general .xdc for the Nexys4 DDR Rev. C
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## Clock signal - uncomment _both_ of these lines to create clk_100mhz
|
||||
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk
|
||||
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk}];
|
||||
|
||||
##Switches
|
||||
|
||||
# set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
|
||||
# set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
|
||||
# set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
|
||||
# set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]
|
||||
# set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]
|
||||
# set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5]
|
||||
# set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]
|
||||
# set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7]
|
||||
# set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8]
|
||||
# set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9]
|
||||
# set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10]
|
||||
# set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11]
|
||||
# set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12]
|
||||
# set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13]
|
||||
# set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14]
|
||||
# set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15]
|
||||
|
||||
|
||||
## LEDs
|
||||
|
||||
set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0]
|
||||
set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1]
|
||||
set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2]
|
||||
set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3]
|
||||
set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4]
|
||||
set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5]
|
||||
set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6]
|
||||
set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7]
|
||||
set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8]
|
||||
set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9]
|
||||
set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10]
|
||||
set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11]
|
||||
set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12]
|
||||
set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13]
|
||||
set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14]
|
||||
set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15]
|
||||
|
||||
# set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { led16_b }]; #IO_L5P_T0_D06_14 Sch=led16_b
|
||||
# set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { led16_g }]; #IO_L10P_T1_D14_14 Sch=led16_g
|
||||
set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led16_r }]; #IO_L11P_T1_SRCC_14 Sch=led16_r
|
||||
# set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led17_b }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b
|
||||
# set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { led17_g }]; #IO_0_14 Sch=led17_g
|
||||
set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led17_r }]; #IO_L11N_T1_SRCC_14 Sch=led17_r
|
||||
|
||||
|
||||
##7 segment display
|
||||
|
||||
set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca
|
||||
set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb
|
||||
set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc
|
||||
set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd
|
||||
set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce
|
||||
set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf
|
||||
set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg
|
||||
|
||||
set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp
|
||||
|
||||
set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
|
||||
set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
|
||||
set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
|
||||
set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
|
||||
set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
|
||||
set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
|
||||
set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6]
|
||||
set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
|
||||
|
||||
|
||||
##Buttons
|
||||
|
||||
# set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn
|
||||
|
||||
# set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btnc }]; #IO_L9P_T1_DQS_14 Sch=btnc
|
||||
# set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { btnu }]; #IO_L4N_T0_D05_14 Sch=btnu
|
||||
# set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { btnl }]; #IO_L12P_T1_MRCC_14 Sch=btnl
|
||||
# set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { btnr }]; #IO_L10N_T1_D15_14 Sch=btnr
|
||||
# set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btnd }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd
|
||||
|
||||
|
||||
##Pmod Headers
|
||||
|
||||
|
||||
##Pmod Header JA
|
||||
|
||||
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L20N_T3_A19_15 Sch=ja[1]
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2]
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L21P_T3_DQS_15 Sch=ja[3]
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L18N_T2_A23_15 Sch=ja[4]
|
||||
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L16N_T2_A27_15 Sch=ja[7]
|
||||
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L16P_T2_A28_15 Sch=ja[8]
|
||||
#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L22N_T3_A16_15 Sch=ja[9]
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L22P_T3_A17_15 Sch=ja[10]
|
||||
|
||||
|
||||
##Pmod Header JB
|
||||
|
||||
#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1]
|
||||
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2]
|
||||
#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3]
|
||||
#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L15P_T2_DQS_15 Sch=jb[4]
|
||||
#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7]
|
||||
#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8]
|
||||
#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_0_15 Sch=jb[9]
|
||||
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10]
|
||||
|
||||
|
||||
##Pmod Header JC
|
||||
|
||||
#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L23N_T3_35 Sch=jc[1]
|
||||
#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L19N_T3_VREF_35 Sch=jc[2]
|
||||
#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L22N_T3_35 Sch=jc[3]
|
||||
#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L19P_T3_35 Sch=jc[4]
|
||||
#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L6P_T0_35 Sch=jc[7]
|
||||
#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22P_T3_35 Sch=jc[8]
|
||||
#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L21P_T3_DQS_35 Sch=jc[9]
|
||||
#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10]
|
||||
|
||||
|
||||
##Pmod Header JD
|
||||
|
||||
#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L21N_T3_DQS_35 Sch=jd[1]
|
||||
#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L17P_T2_35 Sch=jd[2]
|
||||
#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L17N_T2_35 Sch=jd[3]
|
||||
#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L20N_T3_35 Sch=jd[4]
|
||||
#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L15P_T2_DQS_35 Sch=jd[7]
|
||||
#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L20P_T3_35 Sch=jd[8]
|
||||
#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15N_T2_DQS_35 Sch=jd[9]
|
||||
#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10]
|
||||
|
||||
|
||||
##Pmod Header JXADC
|
||||
|
||||
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVDS } [get_ports { xa_n[0] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1]
|
||||
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVDS } [get_ports { xa_p[0] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1]
|
||||
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVDS } [get_ports { xa_n[1] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2]
|
||||
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVDS } [get_ports { xa_p[1] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2]
|
||||
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVDS } [get_ports { xa_n[2] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3]
|
||||
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVDS } [get_ports { xa_p[2] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3]
|
||||
#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVDS } [get_ports { xa_n[3] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4]
|
||||
#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVDS } [get_ports { xa_p[3] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4]
|
||||
|
||||
|
||||
##VGA Connector
|
||||
|
||||
#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0]
|
||||
#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1]
|
||||
#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2]
|
||||
#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3]
|
||||
#
|
||||
#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0]
|
||||
#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1]
|
||||
#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2]
|
||||
#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3]
|
||||
#
|
||||
#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0]
|
||||
#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L4N_T0_35 Sch=vga_b[1]
|
||||
#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2]
|
||||
#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L4P_T0_35 Sch=vga_b[3]
|
||||
|
||||
#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { vga_hs }]; #IO_L4P_T0_15 Sch=vga_hs
|
||||
#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vga_vs }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs
|
||||
|
||||
##Micro SD Connector
|
||||
|
||||
#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset
|
||||
#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd
|
||||
#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { sd_sck }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck
|
||||
#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L16N_T2_35 Sch=sd_cmd
|
||||
#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0]
|
||||
#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1]
|
||||
#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2]
|
||||
#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3]
|
||||
|
||||
|
||||
##Accelerometer
|
||||
|
||||
#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { acl_miso }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso
|
||||
#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { acl_mosi }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi
|
||||
#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { acl_sclk }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk
|
||||
#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { acl_csn }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn
|
||||
#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { acl_int[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1]
|
||||
#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { acl_int[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2]
|
||||
|
||||
|
||||
##Temperature Sensor
|
||||
|
||||
#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { tmp_scl }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl
|
||||
#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { tmp_sda }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda
|
||||
#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { tmp_int }]; #IO_L6N_T0_VREF_15 Sch=tmp_int
|
||||
#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { tmp_ct }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct
|
||||
|
||||
##Omnidirectional Microphone
|
||||
|
||||
#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { m_clk }]; #IO_25_35 Sch=m_clk
|
||||
#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { m_data }]; #IO_L24N_T3_35 Sch=m_data
|
||||
#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { m_lrsel }]; #IO_0_35 Sch=m_lrsel
|
||||
|
||||
|
||||
##PWM Audio Amplifier
|
||||
|
||||
#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { aud_pwm }]; #IO_L4N_T0_15 Sch=aud_pwm
|
||||
#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { aud_sd }]; #IO_L6P_T0_15 Sch=aud_sd
|
||||
|
||||
|
||||
##USB-RS232 Interface
|
||||
|
||||
# set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in
|
||||
# set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out
|
||||
# set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { uart_cts }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts
|
||||
# set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { uart_rts }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts
|
||||
|
||||
##USB HID (PS/2)
|
||||
|
||||
#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { ps2_clk }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk
|
||||
#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { ps2_data }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data
|
||||
|
||||
|
||||
##SMSC Ethernet PHY
|
||||
|
||||
#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc
|
||||
#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio
|
||||
set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn
|
||||
set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { eth_crsdv }]; #IO_L6N_T0_VREF_16 Sch=eth_crs/udv
|
||||
#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr
|
||||
set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0]
|
||||
set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1]
|
||||
set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { eth_txen }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen
|
||||
set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0]
|
||||
set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1]
|
||||
set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { eth_refclk }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk
|
||||
#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { eth_intn }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn
|
||||
|
||||
|
||||
##Quad SPI Flash
|
||||
|
||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
|
||||
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
|
||||
#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_csn }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn
|
||||
|
||||
|
||||
|
|
@ -1,10 +0,0 @@
|
|||
---
|
||||
cores:
|
||||
my_lut_mem:
|
||||
type: lut_mem
|
||||
size: 64
|
||||
|
||||
uart:
|
||||
port: "auto"
|
||||
baudrate: 115200
|
||||
clock_freq: 100000000
|
||||
|
|
@ -1,23 +0,0 @@
|
|||
from manta import Manta
|
||||
from random import randint
|
||||
|
||||
m = Manta("manta.yaml")
|
||||
|
||||
# The API supports reads/writes to single addresses:
|
||||
m.my_lut_mem.write(4, 42)
|
||||
print(m.my_lut_mem.read(4))
|
||||
|
||||
# As it does read/writes to multiple addresses at once:
|
||||
addrs = list(range(m.my_lut_mem.size))
|
||||
m.my_lut_mem.write(addrs, addrs)
|
||||
print(m.my_lut_mem.read(addrs))
|
||||
|
||||
# And here's a little test to write random data and read it back:
|
||||
for addr in range(m.my_lut_mem.size):
|
||||
write_data = randint(0, (2**16)-1)
|
||||
m.my_lut_mem.write(addr, write_data)
|
||||
|
||||
read_data = m.my_lut_mem.read(addr)
|
||||
print(f"test addr: {addr} with data: {hex(write_data)}")
|
||||
print(f" -> correct data received on readback?: {write_data == read_data}")
|
||||
assert write_data == read_data, "data read differs from data written!"
|
||||
|
|
@ -1,73 +0,0 @@
|
|||
`default_nettype none
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module ssd (
|
||||
input wire clk,
|
||||
input wire [31:0] val,
|
||||
output reg [6:0] cat,
|
||||
output reg [7:0] an);
|
||||
|
||||
parameter COUNT_TO = 100000;
|
||||
|
||||
reg [7:0] segment_state = 8'b0000_0001;
|
||||
reg [31:0] segment_counter = 32'b0;
|
||||
reg [3:0] digit;
|
||||
reg [6:0] led_out;
|
||||
|
||||
bto7s mbto7s (
|
||||
.x_in(digit),
|
||||
.s_out(led_out));
|
||||
|
||||
assign cat = ~led_out;
|
||||
assign an = ~segment_state;
|
||||
|
||||
always @(*) begin
|
||||
case(segment_state)
|
||||
8'b0000_0001: digit = val[3:0];
|
||||
8'b0000_0010: digit = val[7:4];
|
||||
8'b0000_0100: digit = val[11:8];
|
||||
8'b0000_1000: digit = val[15:12];
|
||||
8'b0001_0000: digit = val[19:16];
|
||||
8'b0010_0000: digit = val[23:20];
|
||||
8'b0100_0000: digit = val[27:24];
|
||||
8'b1000_0000: digit = val[31:28];
|
||||
default: digit = val[3:0];
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
segment_counter <= segment_counter + 1;
|
||||
|
||||
if (segment_counter == COUNT_TO) begin
|
||||
segment_counter <= 32'd0;
|
||||
segment_state <= {segment_state[6:0], segment_state[7]};
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
module bto7s (
|
||||
input wire [3:0] x_in,
|
||||
output reg [6:0] s_out);
|
||||
|
||||
reg sa, sb, sc, sd, se, sf, sg;
|
||||
assign s_out = {sg, sf, se, sd, sc, sb, sa};
|
||||
|
||||
// array of bits that are "one hot" with numbers 0 through 15
|
||||
reg [15:0] num;
|
||||
genvar i;
|
||||
generate
|
||||
for(i=0; i<16; i=i+1)
|
||||
assign num[i] = (x_in == i);
|
||||
endgenerate
|
||||
|
||||
// map one-hot bits to active segments
|
||||
assign sa = (num & 16'b1101_0111_1110_1101) > 0;
|
||||
assign sb = (num & 16'b0010_0111_1001_1111) > 0;
|
||||
assign sc = (num & 16'b0010_1111_1111_1011) > 0;
|
||||
assign sd = (num & 16'b0111_1011_0110_1101) > 0;
|
||||
assign se = (num & 16'b1111_1101_0100_0101) > 0;
|
||||
assign sf = (num & 16'b1101_1111_0111_0001) > 0;
|
||||
assign sg = (num & 16'b1110_1111_0111_1100) > 0;
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
|
|
@ -1,46 +0,0 @@
|
|||
`default_nettype none
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module top_level (
|
||||
input wire clk,
|
||||
input wire btnc,
|
||||
|
||||
output logic [15:0] led,
|
||||
output logic ca, cb, cc, cd, ce, cf, cg,
|
||||
output logic dp,
|
||||
output logic [7:0] an,
|
||||
|
||||
input wire uart_txd_in,
|
||||
output logic uart_rxd_out
|
||||
);
|
||||
|
||||
manta manta_inst (
|
||||
.clk(clk),
|
||||
|
||||
.rx(uart_txd_in),
|
||||
.tx(uart_rxd_out));
|
||||
|
||||
// Show bus on 7-segment display
|
||||
reg [15:0] addr_latched = 0;
|
||||
reg [15:0] data_latched = 0;
|
||||
reg rw_latched = 0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (manta_inst.brx_my_lut_mem_valid) begin
|
||||
addr_latched <= manta_inst.my_lut_mem_brx_addr;
|
||||
data_latched <= manta_inst.my_lut_mem_brx_data;
|
||||
rw_latched <= manta_inst.my_lut_mem_btx_rw;
|
||||
end
|
||||
end
|
||||
|
||||
ssd ssd (
|
||||
.clk(clk),
|
||||
.val( (addr_latched << 16) | (data_latched) ),
|
||||
.cat({cg,cf,ce,cd,cc,cb,ca}),
|
||||
.an(an));
|
||||
|
||||
assign dp = rw_latched;
|
||||
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
|
|
@ -1,260 +0,0 @@
|
|||
## R1.0 2019-08-27
|
||||
## Updated by jodalyst in 2020-2022
|
||||
## all inputs/outputs changed to lowercase; arrays start with zero.
|
||||
## system clock renamed to clk
|
||||
## ja, jb, jc, jd renamed to 0-7
|
||||
## xa port renamed 0-3
|
||||
## seven segments renamed to a,b,c,d,e,f,dp
|
||||
|
||||
## This file is a general .xdc for the Nexys4 DDR Rev. C
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## Clock signal - uncomment _both_ of these lines to create clk_100mhz
|
||||
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk
|
||||
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk}];
|
||||
|
||||
##Switches
|
||||
|
||||
# set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
|
||||
# set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
|
||||
# set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
|
||||
# set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]
|
||||
# set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]
|
||||
# set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5]
|
||||
# set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]
|
||||
# set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7]
|
||||
# set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8]
|
||||
# set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9]
|
||||
# set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10]
|
||||
# set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11]
|
||||
# set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12]
|
||||
# set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13]
|
||||
# set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14]
|
||||
# set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15]
|
||||
|
||||
|
||||
## LEDs
|
||||
|
||||
set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0]
|
||||
set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1]
|
||||
set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2]
|
||||
set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3]
|
||||
set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4]
|
||||
set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5]
|
||||
set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6]
|
||||
set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7]
|
||||
set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8]
|
||||
set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9]
|
||||
set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10]
|
||||
set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11]
|
||||
set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12]
|
||||
set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13]
|
||||
set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14]
|
||||
set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15]
|
||||
|
||||
#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { led16_b }]; #IO_L5P_T0_D06_14 Sch=led16_b
|
||||
#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { led16_g }]; #IO_L10P_T1_D14_14 Sch=led16_g
|
||||
#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led16_r }]; #IO_L11P_T1_SRCC_14 Sch=led16_r
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led17_b }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b
|
||||
#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { led17_g }]; #IO_0_14 Sch=led17_g
|
||||
#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led17_r }]; #IO_L11N_T1_SRCC_14 Sch=led17_r
|
||||
|
||||
|
||||
##7 segment display
|
||||
|
||||
set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca
|
||||
set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb
|
||||
set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc
|
||||
set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd
|
||||
set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce
|
||||
set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf
|
||||
set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg
|
||||
|
||||
set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp
|
||||
|
||||
set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
|
||||
set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
|
||||
set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
|
||||
set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
|
||||
set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
|
||||
set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
|
||||
set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6]
|
||||
set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
|
||||
|
||||
|
||||
##Buttons
|
||||
|
||||
#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn
|
||||
|
||||
set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btnc }]; #IO_L9P_T1_DQS_14 Sch=btnc
|
||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { btnu }]; #IO_L4N_T0_D05_14 Sch=btnu
|
||||
#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { btnl }]; #IO_L12P_T1_MRCC_14 Sch=btnl
|
||||
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { btnr }]; #IO_L10N_T1_D15_14 Sch=btnr
|
||||
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btnd }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd
|
||||
|
||||
|
||||
##Pmod Headers
|
||||
|
||||
|
||||
##Pmod Header JA
|
||||
|
||||
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L20N_T3_A19_15 Sch=ja[1]
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2]
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L21P_T3_DQS_15 Sch=ja[3]
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L18N_T2_A23_15 Sch=ja[4]
|
||||
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L16N_T2_A27_15 Sch=ja[7]
|
||||
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L16P_T2_A28_15 Sch=ja[8]
|
||||
#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L22N_T3_A16_15 Sch=ja[9]
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L22P_T3_A17_15 Sch=ja[10]
|
||||
|
||||
|
||||
##Pmod Header JB
|
||||
|
||||
#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1]
|
||||
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2]
|
||||
#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3]
|
||||
#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L15P_T2_DQS_15 Sch=jb[4]
|
||||
#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7]
|
||||
#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8]
|
||||
#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_0_15 Sch=jb[9]
|
||||
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10]
|
||||
|
||||
|
||||
##Pmod Header JC
|
||||
|
||||
#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L23N_T3_35 Sch=jc[1]
|
||||
#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L19N_T3_VREF_35 Sch=jc[2]
|
||||
#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L22N_T3_35 Sch=jc[3]
|
||||
#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L19P_T3_35 Sch=jc[4]
|
||||
#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L6P_T0_35 Sch=jc[7]
|
||||
#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22P_T3_35 Sch=jc[8]
|
||||
#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L21P_T3_DQS_35 Sch=jc[9]
|
||||
#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10]
|
||||
|
||||
|
||||
##Pmod Header JD
|
||||
|
||||
#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L21N_T3_DQS_35 Sch=jd[1]
|
||||
#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L17P_T2_35 Sch=jd[2]
|
||||
#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L17N_T2_35 Sch=jd[3]
|
||||
#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L20N_T3_35 Sch=jd[4]
|
||||
#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L15P_T2_DQS_35 Sch=jd[7]
|
||||
#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L20P_T3_35 Sch=jd[8]
|
||||
#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15N_T2_DQS_35 Sch=jd[9]
|
||||
#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10]
|
||||
|
||||
|
||||
##Pmod Header JXADC
|
||||
|
||||
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVDS } [get_ports { xa_n[0] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1]
|
||||
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVDS } [get_ports { xa_p[0] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1]
|
||||
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVDS } [get_ports { xa_n[1] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2]
|
||||
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVDS } [get_ports { xa_p[1] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2]
|
||||
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVDS } [get_ports { xa_n[2] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3]
|
||||
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVDS } [get_ports { xa_p[2] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3]
|
||||
#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVDS } [get_ports { xa_n[3] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4]
|
||||
#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVDS } [get_ports { xa_p[3] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4]
|
||||
|
||||
|
||||
##VGA Connector
|
||||
|
||||
#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0]
|
||||
#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1]
|
||||
#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2]
|
||||
#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3]
|
||||
#
|
||||
#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0]
|
||||
#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1]
|
||||
#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2]
|
||||
#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3]
|
||||
#
|
||||
#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0]
|
||||
#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L4N_T0_35 Sch=vga_b[1]
|
||||
#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2]
|
||||
#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L4P_T0_35 Sch=vga_b[3]
|
||||
|
||||
#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { vga_hs }]; #IO_L4P_T0_15 Sch=vga_hs
|
||||
#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vga_vs }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs
|
||||
|
||||
##Micro SD Connector
|
||||
|
||||
#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset
|
||||
#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd
|
||||
#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { sd_sck }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck
|
||||
#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L16N_T2_35 Sch=sd_cmd
|
||||
#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0]
|
||||
#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1]
|
||||
#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2]
|
||||
#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3]
|
||||
|
||||
|
||||
##Accelerometer
|
||||
|
||||
#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { acl_miso }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso
|
||||
#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { acl_mosi }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi
|
||||
#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { acl_sclk }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk
|
||||
#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { acl_csn }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn
|
||||
#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { acl_int[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1]
|
||||
#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { acl_int[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2]
|
||||
|
||||
|
||||
##Temperature Sensor
|
||||
|
||||
#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { tmp_scl }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl
|
||||
#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { tmp_sda }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda
|
||||
#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { tmp_int }]; #IO_L6N_T0_VREF_15 Sch=tmp_int
|
||||
#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { tmp_ct }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct
|
||||
|
||||
##Omnidirectional Microphone
|
||||
|
||||
#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { m_clk }]; #IO_25_35 Sch=m_clk
|
||||
#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { m_data }]; #IO_L24N_T3_35 Sch=m_data
|
||||
#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { m_lrsel }]; #IO_0_35 Sch=m_lrsel
|
||||
|
||||
|
||||
##PWM Audio Amplifier
|
||||
|
||||
#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { aud_pwm }]; #IO_L4N_T0_15 Sch=aud_pwm
|
||||
#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { aud_sd }]; #IO_L6P_T0_15 Sch=aud_sd
|
||||
|
||||
|
||||
##USB-RS232 Interface
|
||||
|
||||
set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in
|
||||
set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out
|
||||
#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { uart_cts }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts
|
||||
#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { uart_rts }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts
|
||||
|
||||
##USB HID (PS/2)
|
||||
|
||||
#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { ps2_clk }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk
|
||||
#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { ps2_data }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data
|
||||
|
||||
|
||||
##SMSC Ethernet PHY
|
||||
|
||||
#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc
|
||||
#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio
|
||||
#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn
|
||||
#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { eth_crsdv }]; #IO_L6N_T0_VREF_16 Sch=eth_crs/udv
|
||||
#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr
|
||||
#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0]
|
||||
#set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1]
|
||||
#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { eth_txen }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen
|
||||
#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0]
|
||||
#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1]
|
||||
#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { eth_refclk }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk
|
||||
#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { eth_intn }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn
|
||||
|
||||
|
||||
##Quad SPI Flash
|
||||
|
||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
|
||||
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
|
||||
#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_csn }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn
|
||||
|
||||
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
This playback module was generated with Manta v0.0.5 on 19 Jul 2023 at 09:22:12 by fischerm
|
||||
This playback module was generated with Manta v0.0.5 on 19 Jul 2023 at 18:52:11 by fischerm
|
||||
|
||||
If this breaks or if you've got dank formal verification memes, contact fischerm [at] mit.edu
|
||||
|
||||
|
|
|
|||
|
|
@ -1,193 +0,0 @@
|
|||
`default_nettype wire
|
||||
|
||||
// file: divider.sv
|
||||
//
|
||||
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// popopopopopopopopopopop
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||
//----------------------------------------------------------------------------
|
||||
// __ethclk__50.00000______0.000______50.0______151.636_____98.575
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary_________100.000____________0.010
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
module divider
|
||||
|
||||
(// Clock in ports
|
||||
// Clock out ports
|
||||
output ethclk,
|
||||
input clk
|
||||
);
|
||||
// Input buffering
|
||||
//------------------------------------
|
||||
wire clk_divider;
|
||||
wire clk_in2_divider;
|
||||
IBUF clkin1_ibufg
|
||||
(.O (clk_divider),
|
||||
.I (clk));
|
||||
|
||||
|
||||
|
||||
|
||||
// Clocking PRIMITIVE
|
||||
//------------------------------------
|
||||
|
||||
// Instantiation of the MMCM PRIMITIVE
|
||||
// * Unused inputs are tied off
|
||||
// * Unused outputs are labeled unused
|
||||
|
||||
wire ethclk_divider;
|
||||
wire clk_out2_divider;
|
||||
wire clk_out3_divider;
|
||||
wire clk_out4_divider;
|
||||
wire clk_out5_divider;
|
||||
wire clk_out6_divider;
|
||||
wire clk_out7_divider;
|
||||
|
||||
wire [15:0] do_unused;
|
||||
wire drdy_unused;
|
||||
wire psdone_unused;
|
||||
wire locked_int;
|
||||
wire clkfbout_divider;
|
||||
wire clkfbout_buf_divider;
|
||||
wire clkfboutb_unused;
|
||||
wire clkout0b_unused;
|
||||
wire clkout1_unused;
|
||||
wire clkout1b_unused;
|
||||
wire clkout2_unused;
|
||||
wire clkout2b_unused;
|
||||
wire clkout3_unused;
|
||||
wire clkout3b_unused;
|
||||
wire clkout4_unused;
|
||||
wire clkout5_unused;
|
||||
wire clkout6_unused;
|
||||
wire clkfbstopped_unused;
|
||||
wire clkinstopped_unused;
|
||||
|
||||
MMCME2_ADV
|
||||
#(.BANDWIDTH ("OPTIMIZED"),
|
||||
.CLKOUT4_CASCADE ("FALSE"),
|
||||
.COMPENSATION ("ZHOLD"),
|
||||
.STARTUP_WAIT ("FALSE"),
|
||||
.DIVCLK_DIVIDE (1),
|
||||
.CLKFBOUT_MULT_F (10.000),
|
||||
.CLKFBOUT_PHASE (0.000),
|
||||
.CLKFBOUT_USE_FINE_PS ("FALSE"),
|
||||
.CLKOUT0_DIVIDE_F (20.000),
|
||||
.CLKOUT0_PHASE (0.000),
|
||||
.CLKOUT0_DUTY_CYCLE (0.500),
|
||||
.CLKOUT0_USE_FINE_PS ("FALSE"),
|
||||
.CLKIN1_PERIOD (10.000))
|
||||
mmcm_adv_inst
|
||||
// Output clocks
|
||||
(
|
||||
.CLKFBOUT (clkfbout_divider),
|
||||
.CLKFBOUTB (clkfboutb_unused),
|
||||
.CLKOUT0 (ethclk_divider),
|
||||
.CLKOUT0B (clkout0b_unused),
|
||||
.CLKOUT1 (clkout1_unused),
|
||||
.CLKOUT1B (clkout1b_unused),
|
||||
.CLKOUT2 (clkout2_unused),
|
||||
.CLKOUT2B (clkout2b_unused),
|
||||
.CLKOUT3 (clkout3_unused),
|
||||
.CLKOUT3B (clkout3b_unused),
|
||||
.CLKOUT4 (clkout4_unused),
|
||||
.CLKOUT5 (clkout5_unused),
|
||||
.CLKOUT6 (clkout6_unused),
|
||||
// Input clock control
|
||||
.CLKFBIN (clkfbout_buf_divider),
|
||||
.CLKIN1 (clk_divider),
|
||||
.CLKIN2 (1'b0),
|
||||
// Tied to always select the primary input clock
|
||||
.CLKINSEL (1'b1),
|
||||
// Ports for dynamic reconfiguration
|
||||
.DADDR (7'h0),
|
||||
.DCLK (1'b0),
|
||||
.DEN (1'b0),
|
||||
.DI (16'h0),
|
||||
.DO (do_unused),
|
||||
.DRDY (drdy_unused),
|
||||
.DWE (1'b0),
|
||||
// Ports for dynamic phase shift
|
||||
.PSCLK (1'b0),
|
||||
.PSEN (1'b0),
|
||||
.PSINCDEC (1'b0),
|
||||
.PSDONE (psdone_unused),
|
||||
// Other control and status signals
|
||||
.LOCKED (locked_int),
|
||||
.CLKINSTOPPED (clkinstopped_unused),
|
||||
.CLKFBSTOPPED (clkfbstopped_unused),
|
||||
.PWRDWN (1'b0),
|
||||
.RST (1'b0));
|
||||
|
||||
// Clock Monitor clock assigning
|
||||
//--------------------------------------
|
||||
// Output buffering
|
||||
//-----------------------------------
|
||||
|
||||
BUFG clkf_buf
|
||||
(.O (clkfbout_buf_divider),
|
||||
.I (clkfbout_divider));
|
||||
|
||||
BUFG clkout1_buf
|
||||
(.O (ethclk),
|
||||
.I (ethclk_divider));
|
||||
|
||||
endmodule
|
||||
|
||||
`default_nettype none
|
||||
|
|
@ -7,19 +7,12 @@ module top_level (
|
|||
input wire ps2_clk,
|
||||
input wire ps2_data,
|
||||
|
||||
output logic [15:0] led,
|
||||
|
||||
input wire uart_txd_in,
|
||||
output logic uart_rxd_out
|
||||
);
|
||||
|
||||
logic clk_50mhz;
|
||||
divider d (.clk(clk), .ethclk(clk_50mhz));
|
||||
|
||||
assign led = manta_inst.my_logic_analyzer.la_controller.write_pointer;
|
||||
|
||||
manta manta_inst (
|
||||
.clk(clk_50mhz),
|
||||
.clk(clk),
|
||||
|
||||
.rx(uart_txd_in),
|
||||
.tx(uart_rxd_out),
|
||||
|
|
|
|||
|
|
@ -1,98 +1,92 @@
|
|||
## R1.0 2019-08-27
|
||||
## Updated by jodalyst in 2020-2022
|
||||
## all inputs/outputs changed to lowercase; arrays start with zero.
|
||||
## system clock renamed to clk
|
||||
## ja, jb, jc, jd renamed to 0-7
|
||||
## xa port renamed 0-3
|
||||
## seven segments renamed to a,b,c,d,e,f,dp
|
||||
|
||||
## This file is a general .xdc for the Nexys4 DDR Rev. C
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## This file has been modified from the default .xdc provided by Digilent for the Nexys A7
|
||||
|
||||
## Clock signal - uncomment _both_ of these lines to create clk_100mhz
|
||||
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk
|
||||
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk}];
|
||||
|
||||
##Switches
|
||||
|
||||
# set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
|
||||
# set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
|
||||
# set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
|
||||
# set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]
|
||||
# set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]
|
||||
# set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5]
|
||||
# set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]
|
||||
# set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7]
|
||||
# set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8]
|
||||
# set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9]
|
||||
# set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10]
|
||||
# set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11]
|
||||
# set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12]
|
||||
# set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13]
|
||||
# set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14]
|
||||
# set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15]
|
||||
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
|
||||
#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
|
||||
#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
|
||||
#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]
|
||||
#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]
|
||||
#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5]
|
||||
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]
|
||||
#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7]
|
||||
#set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8]
|
||||
#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9]
|
||||
#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10]
|
||||
#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11]
|
||||
#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12]
|
||||
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13]
|
||||
#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14]
|
||||
#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15]
|
||||
|
||||
|
||||
## LEDs
|
||||
|
||||
set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0]
|
||||
set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1]
|
||||
set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2]
|
||||
set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3]
|
||||
set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4]
|
||||
set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5]
|
||||
set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6]
|
||||
set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7]
|
||||
set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8]
|
||||
set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9]
|
||||
set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10]
|
||||
set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11]
|
||||
set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12]
|
||||
set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13]
|
||||
set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14]
|
||||
set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15]
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0]
|
||||
#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1]
|
||||
#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2]
|
||||
#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3]
|
||||
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4]
|
||||
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5]
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6]
|
||||
#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7]
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8]
|
||||
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9]
|
||||
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10]
|
||||
#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11]
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12]
|
||||
#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13]
|
||||
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14]
|
||||
#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15]
|
||||
|
||||
# set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { led16_b }]; #IO_L5P_T0_D06_14 Sch=led16_b
|
||||
# set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { led16_g }]; #IO_L10P_T1_D14_14 Sch=led16_g
|
||||
# set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led16_r }]; #IO_L11P_T1_SRCC_14 Sch=led16_r
|
||||
# set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led17_b }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b
|
||||
# set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { led17_g }]; #IO_0_14 Sch=led17_g
|
||||
# set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led17_r }]; #IO_L11N_T1_SRCC_14 Sch=led17_r
|
||||
#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { led16_b }]; #IO_L5P_T0_D06_14 Sch=led16_b
|
||||
#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { led16_g }]; #IO_L10P_T1_D14_14 Sch=led16_g
|
||||
#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led16_r }]; #IO_L11P_T1_SRCC_14 Sch=led16_r
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led17_b }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b
|
||||
#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { led17_g }]; #IO_0_14 Sch=led17_g
|
||||
#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led17_r }]; #IO_L11N_T1_SRCC_14 Sch=led17_r
|
||||
|
||||
|
||||
##7 segment display
|
||||
|
||||
# set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca
|
||||
# set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb
|
||||
# set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc
|
||||
# set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd
|
||||
# set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce
|
||||
# set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf
|
||||
# set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg
|
||||
#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca
|
||||
#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb
|
||||
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc
|
||||
#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd
|
||||
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce
|
||||
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf
|
||||
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg
|
||||
|
||||
# set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp
|
||||
|
||||
# set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
|
||||
# set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
|
||||
# set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
|
||||
# set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
|
||||
# set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
|
||||
# set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
|
||||
# set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6]
|
||||
# set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
|
||||
#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
|
||||
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
|
||||
#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
|
||||
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
|
||||
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
|
||||
#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6]
|
||||
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
|
||||
|
||||
|
||||
##Buttons
|
||||
|
||||
# set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn
|
||||
#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn
|
||||
|
||||
# set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btnc }]; #IO_L9P_T1_DQS_14 Sch=btnc
|
||||
# set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { btnu }]; #IO_L4N_T0_D05_14 Sch=btnu
|
||||
# set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { btnl }]; #IO_L12P_T1_MRCC_14 Sch=btnl
|
||||
# set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { btnr }]; #IO_L10N_T1_D15_14 Sch=btnr
|
||||
# set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btnd }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd
|
||||
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btnc }]; #IO_L9P_T1_DQS_14 Sch=btnc
|
||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { btnu }]; #IO_L4N_T0_D05_14 Sch=btnu
|
||||
#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { btnl }]; #IO_L12P_T1_MRCC_14 Sch=btnl
|
||||
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { btnr }]; #IO_L10N_T1_D15_14 Sch=btnr
|
||||
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btnd }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd
|
||||
|
||||
|
||||
##Pmod Headers
|
||||
|
|
|
|||
|
|
@ -1,73 +0,0 @@
|
|||
`default_nettype none
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module ssd (
|
||||
input wire clk,
|
||||
input wire [31:0] val,
|
||||
output reg [6:0] cat,
|
||||
output reg [7:0] an);
|
||||
|
||||
parameter COUNT_TO = 100000;
|
||||
|
||||
reg [7:0] segment_state = 8'b0000_0001;
|
||||
reg [31:0] segment_counter = 32'b0;
|
||||
reg [3:0] digit;
|
||||
reg [6:0] led_out;
|
||||
|
||||
bto7s mbto7s (
|
||||
.x_in(digit),
|
||||
.s_out(led_out));
|
||||
|
||||
assign cat = ~led_out;
|
||||
assign an = ~segment_state;
|
||||
|
||||
always @(*) begin
|
||||
case(segment_state)
|
||||
8'b0000_0001: digit = val[3:0];
|
||||
8'b0000_0010: digit = val[7:4];
|
||||
8'b0000_0100: digit = val[11:8];
|
||||
8'b0000_1000: digit = val[15:12];
|
||||
8'b0001_0000: digit = val[19:16];
|
||||
8'b0010_0000: digit = val[23:20];
|
||||
8'b0100_0000: digit = val[27:24];
|
||||
8'b1000_0000: digit = val[31:28];
|
||||
default: digit = val[3:0];
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
segment_counter <= segment_counter + 1;
|
||||
|
||||
if (segment_counter == COUNT_TO) begin
|
||||
segment_counter <= 32'd0;
|
||||
segment_state <= {segment_state[6:0], segment_state[7]};
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
module bto7s (
|
||||
input wire [3:0] x_in,
|
||||
output reg [6:0] s_out);
|
||||
|
||||
reg sa, sb, sc, sd, se, sf, sg;
|
||||
assign s_out = {sg, sf, se, sd, sc, sb, sa};
|
||||
|
||||
// array of bits that are "one hot" with numbers 0 through 15
|
||||
reg [15:0] num;
|
||||
genvar i;
|
||||
generate
|
||||
for(i=0; i<16; i=i+1)
|
||||
assign num[i] = (x_in == i);
|
||||
endgenerate
|
||||
|
||||
// map one-hot bits to active segments
|
||||
assign sa = (num & 16'b1101_0111_1110_1101) > 0;
|
||||
assign sb = (num & 16'b0010_0111_1001_1111) > 0;
|
||||
assign sc = (num & 16'b0010_1111_1111_1011) > 0;
|
||||
assign sd = (num & 16'b0111_1011_0110_1101) > 0;
|
||||
assign se = (num & 16'b1111_1101_0100_0101) > 0;
|
||||
assign sf = (num & 16'b1101_1111_0111_0001) > 0;
|
||||
assign sg = (num & 16'b1110_1111_0111_1100) > 0;
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
|
|
@ -1,16 +1,10 @@
|
|||
## R1.0 2019-08-27
|
||||
## Updated by jodalyst in 2020-2022
|
||||
## all inputs/outputs changed to lowercase; arrays start with zero.
|
||||
## system clock renamed to clk_100mhz
|
||||
## ja, jb, jc, jd renamed to 0-7
|
||||
## xa port renamed 0-3
|
||||
## seven segments renamed to a,b,c,d,e,f,dp
|
||||
|
||||
## This file is a general .xdc for the Nexys4 DDR Rev. C
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## This file has been modified from the default .xdc provided by Digilent for the Nexys A7
|
||||
|
||||
## Clock signal
|
||||
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk_100mhz }]; #IO_L12P_T1_MRCC_35 Sch=clk_100mhz
|
||||
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk_100mhz}];
|
||||
|
|
@ -18,42 +12,42 @@ create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {cl
|
|||
|
||||
##Switches
|
||||
|
||||
# set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
|
||||
# set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
|
||||
# set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
|
||||
# set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]
|
||||
# set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]
|
||||
# set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5]
|
||||
# set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]
|
||||
# set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7]
|
||||
# set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8]
|
||||
# set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9]
|
||||
# set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10]
|
||||
# set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11]
|
||||
# set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12]
|
||||
# set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13]
|
||||
# set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14]
|
||||
# set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15]
|
||||
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
|
||||
#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
|
||||
#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
|
||||
#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]
|
||||
#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]
|
||||
#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5]
|
||||
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]
|
||||
#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7]
|
||||
#set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8]
|
||||
#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9]
|
||||
#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10]
|
||||
#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11]
|
||||
#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12]
|
||||
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13]
|
||||
#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14]
|
||||
#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15]
|
||||
|
||||
|
||||
## LEDs
|
||||
|
||||
# set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0]
|
||||
# set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1]
|
||||
# set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2]
|
||||
# set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3]
|
||||
# set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4]
|
||||
# set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5]
|
||||
# set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6]
|
||||
# set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7]
|
||||
# set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8]
|
||||
# set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9]
|
||||
# set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10]
|
||||
# set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11]
|
||||
# set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12]
|
||||
# set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13]
|
||||
# set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14]
|
||||
# set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15]
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0]
|
||||
#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1]
|
||||
#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2]
|
||||
#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3]
|
||||
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4]
|
||||
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5]
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6]
|
||||
#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7]
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8]
|
||||
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9]
|
||||
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10]
|
||||
#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11]
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12]
|
||||
#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13]
|
||||
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14]
|
||||
#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15]
|
||||
|
||||
#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { led16_b }]; #IO_L5P_T0_D06_14 Sch=led16_b
|
||||
#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { led16_g }]; #IO_L10P_T1_D14_14 Sch=led16_g
|
||||
|
|
@ -65,35 +59,35 @@ create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {cl
|
|||
|
||||
##7 segment display
|
||||
|
||||
# set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca
|
||||
# set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb
|
||||
# set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc
|
||||
# set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd
|
||||
# set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce
|
||||
# set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf
|
||||
# set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg
|
||||
#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca
|
||||
#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb
|
||||
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc
|
||||
#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd
|
||||
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce
|
||||
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf
|
||||
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg
|
||||
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp
|
||||
|
||||
# set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
|
||||
# set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
|
||||
# set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
|
||||
# set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
|
||||
# set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
|
||||
# set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
|
||||
# set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6]
|
||||
# set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
|
||||
#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
|
||||
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
|
||||
#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
|
||||
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
|
||||
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
|
||||
#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6]
|
||||
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
|
||||
|
||||
|
||||
##Buttons
|
||||
|
||||
# set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn
|
||||
#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn
|
||||
|
||||
# set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btnc }]; #IO_L9P_T1_DQS_14 Sch=btnc
|
||||
# set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { btnu }]; #IO_L4N_T0_D05_14 Sch=btnu
|
||||
# set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { btnl }]; #IO_L12P_T1_MRCC_14 Sch=btnl
|
||||
# set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { btnr }]; #IO_L10N_T1_D15_14 Sch=btnr
|
||||
# set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btnd }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd
|
||||
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btnc }]; #IO_L9P_T1_DQS_14 Sch=btnc
|
||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { btnu }]; #IO_L4N_T0_D05_14 Sch=btnu
|
||||
#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { btnl }]; #IO_L12P_T1_MRCC_14 Sch=btnl
|
||||
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { btnr }]; #IO_L10N_T1_D15_14 Sch=btnr
|
||||
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btnd }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd
|
||||
|
||||
|
||||
##Pmod Headers
|
||||
|
|
@ -223,10 +217,10 @@ set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vga_vs
|
|||
|
||||
##USB-RS232 Interface
|
||||
|
||||
# set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in
|
||||
# set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out
|
||||
# set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { uart_cts }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts
|
||||
# set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { uart_rts }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts
|
||||
#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in
|
||||
#set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out
|
||||
#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { uart_cts }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts
|
||||
#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { uart_rts }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts
|
||||
|
||||
##USB HID (PS/2)
|
||||
|
||||
|
|
|
|||
|
|
@ -1,14 +1,13 @@
|
|||
`default_nettype wire
|
||||
|
||||
// file: divider.sv
|
||||
//
|
||||
// file: clk_gen.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
|
|
@ -30,7 +29,7 @@
|
|||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
|
|
@ -44,20 +43,21 @@
|
|||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// popopopopopopopopopopop
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||
//----------------------------------------------------------------------------
|
||||
// __ethclk__50.00000______0.000______50.0______151.636_____98.575
|
||||
// clk_50mhz__50.00000______0.000______50.0______150.541_____99.281
|
||||
// clk_65mhz__65.00000______0.000______50.0______142.278_____99.281
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||
|
|
@ -66,20 +66,21 @@
|
|||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
module divider
|
||||
module clk_gen
|
||||
|
||||
(// Clock in ports
|
||||
// Clock out ports
|
||||
output ethclk,
|
||||
input clk
|
||||
output clk_50mhz,
|
||||
output clk_65mhz,
|
||||
input clk_100mhz
|
||||
);
|
||||
// Input buffering
|
||||
//------------------------------------
|
||||
wire clk_divider;
|
||||
wire clk_in2_divider;
|
||||
wire clk_100mhz_clk_gen;
|
||||
wire clk_in2_clk_gen;
|
||||
IBUF clkin1_ibufg
|
||||
(.O (clk_divider),
|
||||
.I (clk));
|
||||
(.O (clk_100mhz_clk_gen),
|
||||
.I (clk_100mhz));
|
||||
|
||||
|
||||
|
||||
|
|
@ -91,23 +92,22 @@ wire clk_in2_divider;
|
|||
// * Unused inputs are tied off
|
||||
// * Unused outputs are labeled unused
|
||||
|
||||
wire ethclk_divider;
|
||||
wire clk_out2_divider;
|
||||
wire clk_out3_divider;
|
||||
wire clk_out4_divider;
|
||||
wire clk_out5_divider;
|
||||
wire clk_out6_divider;
|
||||
wire clk_out7_divider;
|
||||
wire clk_50mhz_clk_gen;
|
||||
wire clk_65mhz_clk_gen;
|
||||
wire clk_out3_clk_gen;
|
||||
wire clk_out4_clk_gen;
|
||||
wire clk_out5_clk_gen;
|
||||
wire clk_out6_clk_gen;
|
||||
wire clk_out7_clk_gen;
|
||||
|
||||
wire [15:0] do_unused;
|
||||
wire drdy_unused;
|
||||
wire psdone_unused;
|
||||
wire locked_int;
|
||||
wire clkfbout_divider;
|
||||
wire clkfbout_buf_divider;
|
||||
wire clkfbout_clk_gen;
|
||||
wire clkfbout_buf_clk_gen;
|
||||
wire clkfboutb_unused;
|
||||
wire clkout0b_unused;
|
||||
wire clkout1_unused;
|
||||
wire clkout1b_unused;
|
||||
wire clkout2_unused;
|
||||
wire clkout2b_unused;
|
||||
|
|
@ -125,22 +125,26 @@ wire clk_in2_divider;
|
|||
.COMPENSATION ("ZHOLD"),
|
||||
.STARTUP_WAIT ("FALSE"),
|
||||
.DIVCLK_DIVIDE (1),
|
||||
.CLKFBOUT_MULT_F (10.000),
|
||||
.CLKFBOUT_MULT_F (9.750),
|
||||
.CLKFBOUT_PHASE (0.000),
|
||||
.CLKFBOUT_USE_FINE_PS ("FALSE"),
|
||||
.CLKOUT0_DIVIDE_F (20.000),
|
||||
.CLKOUT0_DIVIDE_F (19.500),
|
||||
.CLKOUT0_PHASE (0.000),
|
||||
.CLKOUT0_DUTY_CYCLE (0.500),
|
||||
.CLKOUT0_USE_FINE_PS ("FALSE"),
|
||||
.CLKOUT1_DIVIDE (15),
|
||||
.CLKOUT1_PHASE (0.000),
|
||||
.CLKOUT1_DUTY_CYCLE (0.500),
|
||||
.CLKOUT1_USE_FINE_PS ("FALSE"),
|
||||
.CLKIN1_PERIOD (10.000))
|
||||
mmcm_adv_inst
|
||||
// Output clocks
|
||||
(
|
||||
.CLKFBOUT (clkfbout_divider),
|
||||
.CLKFBOUT (clkfbout_clk_gen),
|
||||
.CLKFBOUTB (clkfboutb_unused),
|
||||
.CLKOUT0 (ethclk_divider),
|
||||
.CLKOUT0 (clk_50mhz_clk_gen),
|
||||
.CLKOUT0B (clkout0b_unused),
|
||||
.CLKOUT1 (clkout1_unused),
|
||||
.CLKOUT1 (clk_65mhz_clk_gen),
|
||||
.CLKOUT1B (clkout1b_unused),
|
||||
.CLKOUT2 (clkout2_unused),
|
||||
.CLKOUT2B (clkout2b_unused),
|
||||
|
|
@ -150,8 +154,8 @@ wire clk_in2_divider;
|
|||
.CLKOUT5 (clkout5_unused),
|
||||
.CLKOUT6 (clkout6_unused),
|
||||
// Input clock control
|
||||
.CLKFBIN (clkfbout_buf_divider),
|
||||
.CLKIN1 (clk_divider),
|
||||
.CLKFBIN (clkfbout_buf_clk_gen),
|
||||
.CLKIN1 (clk_100mhz_clk_gen),
|
||||
.CLKIN2 (1'b0),
|
||||
// Tied to always select the primary input clock
|
||||
.CLKINSEL (1'b1),
|
||||
|
|
@ -181,13 +185,23 @@ wire clk_in2_divider;
|
|||
//-----------------------------------
|
||||
|
||||
BUFG clkf_buf
|
||||
(.O (clkfbout_buf_divider),
|
||||
.I (clkfbout_divider));
|
||||
(.O (clkfbout_buf_clk_gen),
|
||||
.I (clkfbout_clk_gen));
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
BUFG clkout1_buf
|
||||
(.O (ethclk),
|
||||
.I (ethclk_divider));
|
||||
(.O (clk_50mhz),
|
||||
.I (clk_50mhz_clk_gen));
|
||||
|
||||
|
||||
BUFG clkout2_buf
|
||||
(.O (clk_65mhz),
|
||||
.I (clk_65mhz_clk_gen));
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
`default_nettype none
|
||||
|
|
@ -1,176 +0,0 @@
|
|||
// file: clk_wiz_lab3.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||
//----------------------------------------------------------------------------
|
||||
// CLK_OUT1____65.000______0.000______50.0______254.866____297.890
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary_________100.000____________0.010
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
module clk_wiz_lab3
|
||||
(// Clock in ports
|
||||
input clk_in1,
|
||||
// Clock out ports
|
||||
output clk_out1
|
||||
);
|
||||
|
||||
// Input buffering
|
||||
//------------------------------------
|
||||
IBUF clkin1_ibufg
|
||||
(.O (clk_in1_clk_wiz_0),
|
||||
.I (clk_in1));
|
||||
|
||||
|
||||
|
||||
// Clocking PRIMITIVE
|
||||
//------------------------------------
|
||||
|
||||
// Instantiation of the MMCM PRIMITIVE
|
||||
// * Unused inputs are tied off
|
||||
// * Unused outputs are labeled unused
|
||||
wire [15:0] do_unused;
|
||||
wire drdy_unused;
|
||||
wire psdone_unused;
|
||||
wire locked_int;
|
||||
wire clkfbout_clk_wiz_0;
|
||||
wire clkfbout_buf_clk_wiz_0;
|
||||
wire clkfboutb_unused;
|
||||
wire clkout0b_unused;
|
||||
wire clkout1_unused;
|
||||
wire clkout1b_unused;
|
||||
wire clkout2_unused;
|
||||
wire clkout2b_unused;
|
||||
wire clkout3_unused;
|
||||
wire clkout3b_unused;
|
||||
wire clkout4_unused;
|
||||
wire clkout5_unused;
|
||||
wire clkout6_unused;
|
||||
wire clkfbstopped_unused;
|
||||
wire clkinstopped_unused;
|
||||
|
||||
MMCME2_ADV
|
||||
#(.BANDWIDTH ("OPTIMIZED"),
|
||||
.CLKOUT4_CASCADE ("FALSE"),
|
||||
.COMPENSATION ("ZHOLD"),
|
||||
.STARTUP_WAIT ("FALSE"),
|
||||
.DIVCLK_DIVIDE (5),
|
||||
.CLKFBOUT_MULT_F (50.375),
|
||||
.CLKFBOUT_PHASE (0.000),
|
||||
.CLKFBOUT_USE_FINE_PS ("FALSE"),
|
||||
.CLKOUT0_DIVIDE_F (15.500),
|
||||
.CLKOUT0_PHASE (0.000),
|
||||
.CLKOUT0_DUTY_CYCLE (0.500),
|
||||
.CLKOUT0_USE_FINE_PS ("FALSE"),
|
||||
.CLKIN1_PERIOD (10.0))
|
||||
mmcm_adv_inst
|
||||
// Output clocks
|
||||
(
|
||||
.CLKFBOUT (clkfbout_clk_wiz_0),
|
||||
.CLKFBOUTB (clkfboutb_unused),
|
||||
.CLKOUT0 (clk_out1_clk_wiz_0),
|
||||
.CLKOUT0B (clkout0b_unused),
|
||||
.CLKOUT1 (clkout1_unused),
|
||||
.CLKOUT1B (clkout1b_unused),
|
||||
.CLKOUT2 (clkout2_unused),
|
||||
.CLKOUT2B (clkout2b_unused),
|
||||
.CLKOUT3 (clkout3_unused),
|
||||
.CLKOUT3B (clkout3b_unused),
|
||||
.CLKOUT4 (clkout4_unused),
|
||||
.CLKOUT5 (clkout5_unused),
|
||||
.CLKOUT6 (clkout6_unused),
|
||||
// Input clock control
|
||||
.CLKFBIN (clkfbout_buf_clk_wiz_0),
|
||||
.CLKIN1 (clk_in1_clk_wiz_0),
|
||||
.CLKIN2 (1'b0),
|
||||
// Tied to always select the primary input clock
|
||||
.CLKINSEL (1'b1),
|
||||
// Ports for dynamic reconfiguration
|
||||
.DADDR (7'h0),
|
||||
.DCLK (1'b0),
|
||||
.DEN (1'b0),
|
||||
.DI (16'h0),
|
||||
.DO (do_unused),
|
||||
.DRDY (drdy_unused),
|
||||
.DWE (1'b0),
|
||||
// Ports for dynamic phase shift
|
||||
.PSCLK (1'b0),
|
||||
.PSEN (1'b0),
|
||||
.PSINCDEC (1'b0),
|
||||
.PSDONE (psdone_unused),
|
||||
// Other control and status signals
|
||||
.LOCKED (locked_int),
|
||||
.CLKINSTOPPED (clkinstopped_unused),
|
||||
.CLKFBSTOPPED (clkfbstopped_unused),
|
||||
.PWRDWN (1'b0),
|
||||
.RST (1'b0));
|
||||
|
||||
|
||||
|
||||
// Output buffering
|
||||
//-----------------------------------
|
||||
|
||||
BUFG clkf_buf
|
||||
(.O (clkfbout_buf_clk_wiz_0),
|
||||
.I (clkfbout_clk_wiz_0));
|
||||
|
||||
BUFG clkout1_buf
|
||||
(.O (clk_out1),
|
||||
.I (clk_out1_clk_wiz_0));
|
||||
endmodule
|
||||
|
|
@ -1,73 +0,0 @@
|
|||
`default_nettype none
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module ssd (
|
||||
input wire clk,
|
||||
input wire [31:0] val,
|
||||
output reg [6:0] cat,
|
||||
output reg [7:0] an);
|
||||
|
||||
parameter COUNT_TO = 100000;
|
||||
|
||||
reg [7:0] segment_state = 8'b0000_0001;
|
||||
reg [31:0] segment_counter = 32'b0;
|
||||
reg [3:0] digit;
|
||||
reg [6:0] led_out;
|
||||
|
||||
bto7s mbto7s (
|
||||
.x_in(digit),
|
||||
.s_out(led_out));
|
||||
|
||||
assign cat = ~led_out;
|
||||
assign an = ~segment_state;
|
||||
|
||||
always @(*) begin
|
||||
case(segment_state)
|
||||
8'b0000_0001: digit = val[3:0];
|
||||
8'b0000_0010: digit = val[7:4];
|
||||
8'b0000_0100: digit = val[11:8];
|
||||
8'b0000_1000: digit = val[15:12];
|
||||
8'b0001_0000: digit = val[19:16];
|
||||
8'b0010_0000: digit = val[23:20];
|
||||
8'b0100_0000: digit = val[27:24];
|
||||
8'b1000_0000: digit = val[31:28];
|
||||
default: digit = val[3:0];
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
segment_counter <= segment_counter + 1;
|
||||
|
||||
if (segment_counter == COUNT_TO) begin
|
||||
segment_counter <= 32'd0;
|
||||
segment_state <= {segment_state[6:0], segment_state[7]};
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
module bto7s (
|
||||
input wire [3:0] x_in,
|
||||
output reg [6:0] s_out);
|
||||
|
||||
reg sa, sb, sc, sd, se, sf, sg;
|
||||
assign s_out = {sg, sf, se, sd, sc, sb, sa};
|
||||
|
||||
// array of bits that are "one hot" with numbers 0 through 15
|
||||
reg [15:0] num;
|
||||
genvar i;
|
||||
generate
|
||||
for(i=0; i<16; i=i+1)
|
||||
assign num[i] = (x_in == i);
|
||||
endgenerate
|
||||
|
||||
// map one-hot bits to active segments
|
||||
assign sa = (num & 16'b1101_0111_1110_1101) > 0;
|
||||
assign sb = (num & 16'b0010_0111_1001_1111) > 0;
|
||||
assign sc = (num & 16'b0010_1111_1111_1011) > 0;
|
||||
assign sd = (num & 16'b0111_1011_0110_1101) > 0;
|
||||
assign se = (num & 16'b1111_1101_0100_0101) > 0;
|
||||
assign sf = (num & 16'b1101_1111_0111_0001) > 0;
|
||||
assign sg = (num & 16'b1110_1111_0111_1100) > 0;
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
|
|
@ -1,25 +1,22 @@
|
|||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
module top_level(
|
||||
input wire clk_100mhz,
|
||||
module top_level (
|
||||
input wire clk_100mhz,
|
||||
|
||||
output logic [3:0] vga_r, vga_g, vga_b,
|
||||
output logic vga_hs, vga_vs,
|
||||
input wire uart_txd_in,
|
||||
output logic uart_rxd_out,
|
||||
|
||||
input wire btnc,
|
||||
output logic [15:0] led,
|
||||
output logic ca, cb, cc, cd, ce, cf, cg, dp,
|
||||
output logic [7:0] an,
|
||||
|
||||
input wire uart_txd_in,
|
||||
output logic uart_rxd_out);
|
||||
output logic [3:0] vga_r, vga_g, vga_b,
|
||||
output logic vga_hs, vga_vs);
|
||||
|
||||
// Clock generation
|
||||
logic clk_65mhz;
|
||||
|
||||
clk_wiz_lab3 clk_gen(
|
||||
.clk_in1(clk_100mhz),
|
||||
.clk_out1(clk_65mhz));
|
||||
clk_gen gen(
|
||||
.clk_100mhz(clk_100mhz),
|
||||
.clk_50mhz(),
|
||||
.clk_65mhz(clk_65mhz));
|
||||
|
||||
// VGA signals
|
||||
logic [10:0] hcount;
|
||||
|
|
@ -46,11 +43,13 @@
|
|||
vcount_pipe[0] <= vcount;
|
||||
hsync_pipe[0] <= hsync;
|
||||
vsync_pipe[0] <= vsync;
|
||||
for (int i=1; i<4; i = i+1)begin
|
||||
blank_pipe[0] <= blank;
|
||||
for (int i=1; i<2; i = i+1)begin
|
||||
hcount_pipe[i] <= hcount_pipe[i-1];
|
||||
vcount_pipe[i] <= vcount_pipe[i-1];
|
||||
hsync_pipe[i] <= hsync_pipe[i-1];
|
||||
vsync_pipe[i] <= vsync_pipe[i-1];
|
||||
blank_pipe[i] <= blank_pipe[i-1];
|
||||
end
|
||||
end
|
||||
|
||||
|
|
@ -92,26 +91,6 @@
|
|||
assign vga_hs = ~hsync_pipe[1];
|
||||
assign vga_vs = ~vsync_pipe[1];
|
||||
|
||||
// Show bus on 7-segment display
|
||||
reg [15:0] addr_latched = 0;
|
||||
reg [15:0] data_latched = 0;
|
||||
reg rw_latched = 0;
|
||||
|
||||
always @(posedge clk_65mhz) begin
|
||||
if (manta_inst.brx_image_mem_valid) begin
|
||||
addr_latched <= manta_inst.brx_image_mem_addr;
|
||||
data_latched <= manta_inst.brx_image_mem_data;
|
||||
rw_latched <= manta_inst.brx_image_mem_rw;
|
||||
end
|
||||
end
|
||||
|
||||
ssd ssd (
|
||||
.clk(clk_65mhz),
|
||||
.val( (addr_latched << 16) | (data_latched) ),
|
||||
.cat({cg,cf,ce,cd,cc,cb,ca}),
|
||||
.an(an));
|
||||
|
||||
assign dp = rw_latched;
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
endmodule
|
||||
`default_nettype wire
|
||||
|
|
|
|||
|
|
@ -1,16 +1,10 @@
|
|||
## R1.0 2019-08-27
|
||||
## Updated by jodalyst in 2020-2022
|
||||
## all inputs/outputs changed to lowercase; arrays start with zero.
|
||||
## system clock renamed to clk_100mhz
|
||||
## ja, jb, jc, jd renamed to 0-7
|
||||
## xa port renamed 0-3
|
||||
## seven segments renamed to a,b,c,d,e,f,dp
|
||||
|
||||
## This file is a general .xdc for the Nexys4 DDR Rev. C
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## This file has been modified from the default .xdc provided by Digilent for the Nexys A7
|
||||
|
||||
## Clock signal
|
||||
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk_100mhz }]; #IO_L12P_T1_MRCC_35 Sch=clk_100mhz
|
||||
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk_100mhz}];
|
||||
|
|
@ -18,42 +12,42 @@ create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {cl
|
|||
|
||||
##Switches
|
||||
|
||||
# set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
|
||||
# set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
|
||||
# set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
|
||||
# set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]
|
||||
# set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]
|
||||
# set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5]
|
||||
# set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]
|
||||
# set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7]
|
||||
# set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8]
|
||||
# set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9]
|
||||
# set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10]
|
||||
# set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11]
|
||||
# set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12]
|
||||
# set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13]
|
||||
# set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14]
|
||||
# set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15]
|
||||
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
|
||||
#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
|
||||
#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
|
||||
#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]
|
||||
#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]
|
||||
#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5]
|
||||
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]
|
||||
#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7]
|
||||
#set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8]
|
||||
#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9]
|
||||
#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10]
|
||||
#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11]
|
||||
#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12]
|
||||
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13]
|
||||
#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14]
|
||||
#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15]
|
||||
|
||||
|
||||
## LEDs
|
||||
|
||||
set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0]
|
||||
set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1]
|
||||
set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2]
|
||||
set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3]
|
||||
set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4]
|
||||
set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5]
|
||||
set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6]
|
||||
set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7]
|
||||
set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8]
|
||||
set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9]
|
||||
set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10]
|
||||
set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11]
|
||||
set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12]
|
||||
set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13]
|
||||
set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14]
|
||||
set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15]
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0]
|
||||
#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1]
|
||||
#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2]
|
||||
#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3]
|
||||
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4]
|
||||
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5]
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6]
|
||||
#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7]
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8]
|
||||
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9]
|
||||
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10]
|
||||
#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11]
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12]
|
||||
#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13]
|
||||
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14]
|
||||
#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15]
|
||||
|
||||
#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { led16_b }]; #IO_L5P_T0_D06_14 Sch=led16_b
|
||||
#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { led16_g }]; #IO_L10P_T1_D14_14 Sch=led16_g
|
||||
|
|
@ -65,35 +59,35 @@ set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15
|
|||
|
||||
##7 segment display
|
||||
|
||||
set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca
|
||||
set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb
|
||||
set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc
|
||||
set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd
|
||||
set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce
|
||||
set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf
|
||||
set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg
|
||||
#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca
|
||||
#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb
|
||||
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc
|
||||
#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd
|
||||
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce
|
||||
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf
|
||||
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg
|
||||
|
||||
set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp
|
||||
|
||||
set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
|
||||
set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
|
||||
set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
|
||||
set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
|
||||
set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
|
||||
set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
|
||||
set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6]
|
||||
set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
|
||||
#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
|
||||
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
|
||||
#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
|
||||
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
|
||||
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
|
||||
#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6]
|
||||
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
|
||||
|
||||
|
||||
##Buttons
|
||||
|
||||
# set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn
|
||||
#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn
|
||||
|
||||
set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btnc }]; #IO_L9P_T1_DQS_14 Sch=btnc
|
||||
# set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { btnu }]; #IO_L4N_T0_D05_14 Sch=btnu
|
||||
# set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { btnl }]; #IO_L12P_T1_MRCC_14 Sch=btnl
|
||||
# set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { btnr }]; #IO_L10N_T1_D15_14 Sch=btnr
|
||||
# set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btnd }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd
|
||||
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btnc }]; #IO_L9P_T1_DQS_14 Sch=btnc
|
||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { btnu }]; #IO_L4N_T0_D05_14 Sch=btnu
|
||||
#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { btnl }]; #IO_L12P_T1_MRCC_14 Sch=btnl
|
||||
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { btnr }]; #IO_L10N_T1_D15_14 Sch=btnr
|
||||
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btnd }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd
|
||||
|
||||
|
||||
##Pmod Headers
|
||||
|
|
|
|||
|
|
@ -63,7 +63,6 @@ nav:
|
|||
- IO Core: io_core.md
|
||||
- Logic Analyzer Core: logic_analyzer_core.md
|
||||
- Block Memory Core: block_memory_core.md
|
||||
- LUT Memory Core: lut_memory_core.md
|
||||
- Tutorials:
|
||||
- Tutorial 0 - IO Core: tutorial_0.md
|
||||
- Tutorial 1 - Logic Analyzer Core: tutorial_1.md
|
||||
|
|
|
|||
|
|
@ -3,7 +3,6 @@ from .hdl_utils import *
|
|||
from .la_core import *
|
||||
from .io_core import *
|
||||
from .block_mem_core import *
|
||||
from .lut_mem_core import *
|
||||
|
||||
# External Dependencies
|
||||
from sys import argv
|
||||
|
|
@ -47,9 +46,6 @@ class Manta:
|
|||
elif core["type"] == "io":
|
||||
new_core = IOCore(core, core_name, base_addr, self.interface)
|
||||
|
||||
elif core["type"] == "lut_mem":
|
||||
new_core = LUTMemoryCore(core, core_name, base_addr, self.interface)
|
||||
|
||||
elif core["type"] == "block_mem":
|
||||
new_core = BlockMemoryCore(core, core_name, base_addr, self.interface)
|
||||
|
||||
|
|
|
|||
|
|
@ -1,47 +0,0 @@
|
|||
from ..hdl_utils import *
|
||||
|
||||
class LUTMemoryCore:
|
||||
def __init__(self, config, name, base_addr, interface):
|
||||
self.name = name
|
||||
self.base_addr = base_addr
|
||||
self.interface = interface
|
||||
|
||||
# Warn if unrecognized options have been given
|
||||
for option in config:
|
||||
if option not in ["type", "size"]:
|
||||
print(f"Warning: Ignoring unrecognized option '{option}' in LUT Memory '{self.name}'")
|
||||
|
||||
assert "size" in config, "Size not specified for LUT RAM core."
|
||||
assert config["size"] > 0, "LUT RAM must have positive size."
|
||||
assert isinstance(config["size"], int), "LUT RAM must have integer size."
|
||||
self.size = config["size"]
|
||||
|
||||
self.max_addr = self.base_addr + self.size - 1
|
||||
|
||||
def hdl_inst(self):
|
||||
inst = VerilogManipulator("lut_mem_core/lut_mem_inst_tmpl.v")
|
||||
inst.sub(self.size, "/* DEPTH */")
|
||||
inst.sub(self.name, "/* INST_NAME */")
|
||||
return inst.get_hdl()
|
||||
|
||||
def hdl_def(self):
|
||||
return VerilogManipulator("lut_mem_core/lut_mem.v").get_hdl()
|
||||
|
||||
def hdl_top_level_ports(self):
|
||||
# no top_level connections since this core just lives on the bus
|
||||
return ""
|
||||
|
||||
def get_physical_addr(self, addr):
|
||||
if isinstance(addr, int):
|
||||
return addr + self.base_addr
|
||||
|
||||
elif isinstance(addr, list):
|
||||
return [a + self.base_addr for a in addr]
|
||||
|
||||
raise ValueError("Read address must be integer or list of integers.")
|
||||
|
||||
def read(self, addr):
|
||||
return self.interface.read(self.get_physical_addr(addr))
|
||||
|
||||
def write(self, addr, data):
|
||||
return self.interface.write(self.get_physical_addr(addr), data)
|
||||
|
|
@ -1,43 +0,0 @@
|
|||
`default_nettype none
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module lut_mem (
|
||||
input wire clk,
|
||||
|
||||
// input port
|
||||
input wire [15:0] addr_i,
|
||||
input wire [15:0] data_i,
|
||||
input wire rw_i,
|
||||
input wire valid_i,
|
||||
|
||||
// output port
|
||||
output reg [15:0] addr_o,
|
||||
output reg [15:0] data_o,
|
||||
output reg rw_o,
|
||||
output reg valid_o);
|
||||
|
||||
parameter DEPTH = 8;
|
||||
parameter BASE_ADDR = 0;
|
||||
parameter READ_ONLY = 0;
|
||||
reg [15:0] mem [DEPTH-1:0];
|
||||
|
||||
always @(posedge clk) begin
|
||||
addr_o <= addr_i;
|
||||
data_o <= data_i;
|
||||
rw_o <= rw_i;
|
||||
valid_o <= valid_i;
|
||||
|
||||
|
||||
if(valid_i) begin
|
||||
// check if address is valid
|
||||
if( (addr_i >= BASE_ADDR) && (addr_i <= BASE_ADDR + DEPTH - 1) ) begin
|
||||
|
||||
// read/write
|
||||
if (rw_i && !READ_ONLY) mem[addr_i - BASE_ADDR] <= data_i;
|
||||
else data_o <= mem[addr_i - BASE_ADDR];
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
|
|
@ -1,12 +0,0 @@
|
|||
lut_mem #(.DEPTH(/* DEPTH */)) /* INST_NAME */ (
|
||||
.clk(clk),
|
||||
|
||||
.addr_i(),
|
||||
.data_i(),
|
||||
.rw_i(),
|
||||
.valid_i(),
|
||||
|
||||
.addr_o(),
|
||||
.data_o(),
|
||||
.rw_o(),
|
||||
.valid_o());
|
||||
|
|
@ -1,196 +0,0 @@
|
|||
`default_nettype none
|
||||
|
||||
`define CP 10
|
||||
`define HCP 5
|
||||
|
||||
module lut_mem_tb;
|
||||
// https://www.youtube.com/watch?v=WCOAr-96bGc
|
||||
|
||||
//boilerplate
|
||||
logic clk;
|
||||
integer test_num;
|
||||
|
||||
// tb --> mem_1 signals
|
||||
logic [15:0] tb_mem_1_addr;
|
||||
logic [15:0] tb_mem_1_data;
|
||||
logic tb_mem_1_rw;
|
||||
logic tb_mem_1_valid;
|
||||
|
||||
lut_mem #(
|
||||
.DEPTH(8),
|
||||
.BASE_ADDR(0)
|
||||
) mem_1 (
|
||||
.clk(clk),
|
||||
.addr_i(tb_mem_1_addr),
|
||||
.data_i(tb_mem_1_data),
|
||||
.rw_i(tb_mem_1_rw),
|
||||
.valid_i(tb_mem_1_valid),
|
||||
|
||||
.addr_o(mem_1_mem_2_addr),
|
||||
.data_o(mem_1_mem_2_data),
|
||||
.rw_o(mem_1_mem_2_rw),
|
||||
.valid_o(mem_1_mem_2_valid)
|
||||
);
|
||||
|
||||
// mem_1 --> mem_2 signals
|
||||
logic [15:0] mem_1_mem_2_addr;
|
||||
logic [15:0] mem_1_mem_2_data;
|
||||
logic mem_1_mem_2_rw;
|
||||
logic mem_1_mem_2_valid;
|
||||
|
||||
lut_mem #(
|
||||
.DEPTH(8),
|
||||
.BASE_ADDR(8)
|
||||
) mem_2 (
|
||||
.clk(clk),
|
||||
.addr_i(mem_1_mem_2_addr),
|
||||
.data_i(mem_1_mem_2_data),
|
||||
.rw_i(mem_1_mem_2_rw),
|
||||
.valid_i(mem_1_mem_2_valid),
|
||||
|
||||
.addr_o(mem_2_mem_3_addr),
|
||||
.data_o(mem_2_mem_3_data),
|
||||
.rw_o(mem_2_mem_3_rw),
|
||||
.valid_o(mem_2_mem_3_valid)
|
||||
);
|
||||
|
||||
// mem_2 --> mem_3 signals
|
||||
logic [15:0] mem_2_mem_3_addr;
|
||||
logic [15:0] mem_2_mem_3_data;
|
||||
logic mem_2_mem_3_rw;
|
||||
logic mem_2_mem_3_valid;
|
||||
|
||||
lut_mem #(
|
||||
.DEPTH(8),
|
||||
.BASE_ADDR(16)
|
||||
) mem_3 (
|
||||
.clk(clk),
|
||||
.addr_i(mem_2_mem_3_addr),
|
||||
.data_i(mem_2_mem_3_data),
|
||||
.rw_i(mem_2_mem_3_rw),
|
||||
.valid_i(mem_2_mem_3_valid),
|
||||
|
||||
.addr_o(mem_3_tb_addr),
|
||||
.data_o(mem_3_tb_data),
|
||||
.rw_o(mem_3_tb_rw),
|
||||
.valid_o(mem_3_tb_valid)
|
||||
);
|
||||
|
||||
// mem_3 --> tb signals
|
||||
logic [15:0] mem_3_tb_addr;
|
||||
logic [15:0] mem_3_tb_data;
|
||||
logic mem_3_tb_rw;
|
||||
logic mem_3_tb_valid;
|
||||
|
||||
always begin
|
||||
#`HCP
|
||||
clk = !clk;
|
||||
end
|
||||
|
||||
initial begin
|
||||
$dumpfile("lut_mem.vcd");
|
||||
$dumpvars(0, lut_mem_tb);
|
||||
|
||||
// setup and reset
|
||||
clk = 0;
|
||||
test_num = 0;
|
||||
#`HCP
|
||||
|
||||
// throw some nonzero data in the memories just so we know that we're pulling from the right ones
|
||||
mem_1.mem[0] = 16'h0000;
|
||||
mem_1.mem[1] = 16'h0001;
|
||||
mem_1.mem[2] = 16'h0002;
|
||||
mem_1.mem[3] = 16'h0003;
|
||||
mem_1.mem[4] = 16'h0004;
|
||||
mem_1.mem[5] = 16'h0005;
|
||||
mem_1.mem[6] = 16'h0006;
|
||||
mem_1.mem[7] = 16'h0007;
|
||||
|
||||
mem_2.mem[0] = 16'h0008;
|
||||
mem_2.mem[1] = 16'h0009;
|
||||
mem_2.mem[2] = 16'h000A;
|
||||
mem_2.mem[3] = 16'h000B;
|
||||
mem_2.mem[4] = 16'h000C;
|
||||
mem_2.mem[5] = 16'h000D;
|
||||
mem_2.mem[6] = 16'h000E;
|
||||
mem_2.mem[7] = 16'h000F;
|
||||
|
||||
mem_3.mem[0] = 16'h0010;
|
||||
mem_3.mem[1] = 16'h0011;
|
||||
mem_3.mem[2] = 16'h0012;
|
||||
mem_3.mem[3] = 16'h0013;
|
||||
mem_3.mem[4] = 16'h0014;
|
||||
mem_3.mem[5] = 16'h0015;
|
||||
mem_3.mem[6] = 16'h0016;
|
||||
mem_3.mem[7] = 16'h0017;
|
||||
|
||||
tb_mem_1_addr = 0;
|
||||
tb_mem_1_data = 0;
|
||||
tb_mem_1_rw = 0;
|
||||
tb_mem_1_valid = 0;
|
||||
|
||||
#(10*`CP);
|
||||
|
||||
/* ==== Test 1 Begin ==== */
|
||||
$display("\n=== test 1: read from 0x0001 for baseline functionality ===");
|
||||
test_num = 1;
|
||||
|
||||
// TODO: make this check that all bus outputs are 0
|
||||
|
||||
// assert(req_addr == 16'h1234) else $fatal(0, "incorrect addr!");
|
||||
// assert(req_data == 16'h5678) else $fatal(0, "incorrect data!");
|
||||
// assert(req_rw == 1) else $fatal(0, "incorrect rw!");
|
||||
// assert(bridge_rx_uut.state != bridge_rx_uut.ERROR) else $fatal(0, "in error state after transmission");
|
||||
|
||||
tb_mem_1_addr = 16'h0001;
|
||||
tb_mem_1_valid = 1;
|
||||
tb_mem_1_rw = 0;
|
||||
#`CP;
|
||||
tb_mem_1_valid = 0;
|
||||
|
||||
#(10*`CP);
|
||||
/* ==== Test 1 End ==== */
|
||||
|
||||
/* ==== Test 2 Begin ==== */
|
||||
$display("\n=== test 2: read from 0x0012 for baseline functionality ===");
|
||||
test_num = 2;
|
||||
|
||||
tb_mem_1_addr = 16'h0012;
|
||||
tb_mem_1_valid = 1;
|
||||
tb_mem_1_rw = 0;
|
||||
#`CP;
|
||||
tb_mem_1_valid = 0;
|
||||
#(10*`CP);
|
||||
/* ==== Test 2 End ==== */
|
||||
|
||||
/* ==== Test 3 Begin ==== */
|
||||
$display("\n=== test 3: write to 0x0012 for baseline functionality ===");
|
||||
test_num = 3;
|
||||
|
||||
tb_mem_1_addr = 16'h0012;
|
||||
tb_mem_1_data = 16'h0069;
|
||||
tb_mem_1_valid = 1;
|
||||
tb_mem_1_rw = 1;
|
||||
#`CP;
|
||||
tb_mem_1_valid = 0;
|
||||
tb_mem_1_rw = 0;
|
||||
#(10*`CP);
|
||||
/* ==== Test 3 End ==== */
|
||||
|
||||
/* ==== Test 4 Begin ==== */
|
||||
$display("\n=== test 4: read from 0x0012 for baseline functionality ===");
|
||||
test_num = 4;
|
||||
|
||||
tb_mem_1_addr = 16'h000A;
|
||||
tb_mem_1_valid = 1;
|
||||
tb_mem_1_rw = 0;
|
||||
#`CP;
|
||||
tb_mem_1_valid = 0;
|
||||
#(10*`CP);
|
||||
/* ==== Test 3 End ==== */
|
||||
|
||||
$finish();
|
||||
end
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
Loading…
Reference in New Issue