update playback module, needs pipelining

.github/workflows/run_tests.yml

@@ -23,7 +23,7 @@ jobs:
           export DEB_PYTHON_INSTALL_LAYOUT=deb_system
 
           # Install Manta, with optional dev-only dependencies
-          python -m pip install ".[dev]"
+          python3 -m pip install ".[dev]"
 
       - name: Run tests
         run:  |

src/manta/cli.py

@@ -6,34 +6,21 @@ from pkg_resources import get_distribution
 version = "v" + get_distribution("manta").version
 
 logo = f"""
-\033[96m               (\.-./)
-\033[96m               /     \\
-\033[96m             .'   :   '.
-\033[96m        _.-'`     '     `'-._       \033[34;49;1m | \033[34;49;1m Manta {version} \033[00m
-\033[96m     .-'          :          '-.    \033[34;49;1m | \033[34;49;3m An In-Situ Debugging Tool for Programmable Hardware \033[00m
-\033[96m   ,'_.._         .         _.._',  \033[34;49;1m | \033[34;49m https://github.com/fischermoseley/manta \033[00m
-\033[96m   '`    `'-.     '     .-'`
-\033[96m             '.   :   .'            \033[34;49;1m | \033[34;49;3m Originally created by Fischer Moseley \033[00m
-\033[96m               \_. ._/
-\033[96m         \       |^|
-\033[96m          |      | ;
-\033[96m          \\'.___.' /
-\033[96m           '-....-'  \033[00m
+Manta {version}
 
-Supported commands:
-    gen      [config_file] [verilog_file]                           generate a verilog file specifying the Manta module from a given configuration file, and save to the provided path
-    capture  [config_file] [la_core_name] [vcd_file] [verilog_file] start a capture on the specified core, and save the results to a .vcd or .v file at the provided path(s)
-    ports                                                           list all available serial ports
-    help, ray                                                       display this splash screen (hehe...splash screen)
+Usage:
+    gen     [config_file] [verilog_file]                           Generate a verilog file specifying the Manta module from a given configuration file, and save to the provided path
+    capture [config_file] [la_core_name] [vcd_file] [verilog_file] Start a capture on the specified core, and save the results to a .vcd or .v file at the provided path(s)
+    ports                                                          List all available serial ports
+    help                                                           Display this help menu
 """
 
-
 def help():
     print(logo)
 
 
 def wrong_args():
-    raise ValueError('Wrong number of arguments, run "manta help" for usage.')
+    print('Wrong number of arguments, run "manta help" for usage.')
 
 
 def gen(config_path, output_path):

src/manta/logic_analyzer_core.py

@@ -488,15 +488,15 @@ class LogicAnalyzerCapture:
         return LogicAnalyzerPlayback(self.data, self.config)
 
     def export_playback_verilog(self, path):
-        la = LogicAnalyzerPlayback(self.data, self.config)
+        lap = LogicAnalyzerPlayback(self.data, self.config)
         from amaranth.back import verilog
 
         with open(path, "w") as f:
             f.write(
                 verilog.convert(
-                    la,
+                    lap,
                     name="logic_analyzer_playback",
-                    ports=la.get_top_level_ports(),
+                    ports=lap.get_top_level_ports(),
                     strip_internal_attrs=True,
                 )
             )
@@ -508,8 +508,13 @@ class LogicAnalyzerPlayback(Elaboratable):
         self.config = config
 
         # State Machine
-        self.enable = Signal(1)
+        self.start = Signal(1)
         self.done = Signal(1)
+        self.states = {
+            "IDLE" : 0,
+            "RUN" : 1,
+            "DONE" : 2
+        }
 
         # Top-Level Probe signals
         self.top_level_probes = {}
@@ -530,6 +535,31 @@ class LogicAnalyzerPlayback(Elaboratable):
         m.submodules["mem"] = self.mem
         m.d.comb += self.read_port.en.eq(1)
 
+        state = Signal(range(len(self.states)))
+        addr = self.read_port.addr
+
+        # Run state machine
+        with m.If(state == self.states["IDLE"]):
+            with m.If(self.start):
+                m.d.sync += state.eq(self.states["RUN"])
+                m.d.sync += addr.eq(0)
+
+        with m.Elif(state == self.states["RUN"]):
+            with m.If(addr < self.config["sample_depth"]):
+                m.d.sync += addr.eq(addr + 1)
+
+            with m.Else():
+                m.d.sync += state.eq(self.states["DONE"])
+                m.d.sync += self.done.eq(1)
+
+
+        with m.Else(state == self.states["DONE"]):
+            with m.If(self.start):
+                m.d.sync += self.done.eq(0)
+                m.d.sync += state.eq(self.states["RUN"])
+                m.d.sync += addr.eq(0)
+
+
         # Assign the probe values by part-selecting from the data port
         lower = 0
         for name, width in reversed(self.config["probes"].items()):
@@ -544,15 +574,5 @@ class LogicAnalyzerPlayback(Elaboratable):
 
             lower += width
 
-        # Iterate through the samples if saved
-        with m.If((self.enable) & (~self.done)):
-            with m.If(self.read_port.addr < (self.config["sample_depth"] - 1)):
-                m.d.sync += self.read_port.addr.eq(self.read_port.addr + 1)
-
-            with m.Else():
-                m.d.sync += self.done.eq(1)
-
-        return m
-
     def get_top_level_ports(self):
         return [self.enable, self.done] + list(self.top_level_probes.values())